I’m developping an ISL79987(4ch input video decoder) MIPI-CSI 2 driver for Jetson Orin Nano.
Out System information :
1.SOM : Jetson Orin Nano
2.Carrier Board : Custom Board
3.Camera : Analog type Camera 1 ea.(final aim is 4 ea)
4.We use the CSI 0 .
5.JetPack Version : 5.1.1(L4T : 35.3.1)
I back ported the driver from Linux 6.x to Linux 5.10 version(L4t kernel version), the driver probe successfully, and it registers the device to sysfs as video node without errors (Creating the /dev/video0)
But i could not capture the image.
since it’s Orin Nano, please aware there’s polarity swap, i.e. CSI0 D1 and CSI1 D0 P/N will always been swizzled for P/N.
you may use device tree property, lane_polarity to configure a polarity swap on any lane.
please also review the schematic for setting this accordingly.
* Based on the camera connector pin.
* CSIx_D0 | CSIx_D1 | CSI(X+1)_D0 | CSI(X+1)CSIx_D1
* LSB | BIT1 | BIT2 | MSB
* if there is a polarity swap on any lane, the bit corrsponding
* to the lane should be set
* e.g. polarity swap on CSIx_D0 only -> lane_polarity = "1"; 0001
* e.g. polarity swap on CSIx_D1 and CSI(X+1)_D0 -> lane_polarity = "6"; 0110
there’s PHY interrupt, the error code 0x1 means LP sequence error has detected on clock lane.
normally, it should follow by LP11->LP01->LP00->LP11 sequence. it’s more like an issue from camera side.
please see-also developer guide, Property-Value Pairs, you may tune the cil_settletime settings.
yes… they’re using the same port index. but Orin Nano has less CSI lanes.
you may update cil_settletime settings in the device tree.
you could recompile the device tree binary from source.
or, you could disassembler the dtb file into text file for edit. for example, $ dtc -I dtb -O dts -o temp.dts tegra234-xxx.dtb, and then, convert the DTS into a DTB file, $ dtc -I dts -O dtb -o output.dtb temp.dts
for loading new device tree, you should edit /boot/extlinux/extlinux.conf to create a new label, with new FDT entry for loading a new dtb file.