MIPI-CSI2 in jetson orin nano

Hi all.
I’m developping an ISL79987(4ch input video decoder) MIPI-CSI 2 driver for Jetson Orin Nano.
Out System information :
1.SOM : Jetson Orin Nano
2.Carrier Board : Custom Board
3.Camera : Analog type Camera 1 ea.(final aim is 4 ea)
4.We use the CSI 0 .
5.JetPack Version : 5.1.1(L4T : 35.3.1)

I back ported the driver from Linux 6.x to Linux 5.10 version(L4t kernel version), the driver probe successfully, and it registers the device to sysfs as video node without errors (Creating the /dev/video0)
But i could not capture the image.

Description of DT :
/ {

    tegra-capture-vi {
            status = "okay";
            num-channels = <1>;
            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    port@0 {
                            status = "okay";
                            reg = <0>;
                            isl79987_vi_in0: endpoint {
                                    status = "okay";
                                    port-index = <0>;
                                    bus-width = <1>;
                                    remote-endpoint = <&isl79987_csi_out0>;
                            };
                    };
            };
    };

    host1x@13e00000
    {
            nvcsi@15a00000
            {
                    num-channels = <1>;
                    #address-cells = <1>;
                    #size-cells = <0>;
                    status = "okay";

                    channel@0 {
                            status = "okay";
                            reg = <0>;
                            ports {
                                    status = "okay";
                                    #address-cells = <1>;
                                    #size-cells = <0>;
                                    port@0 {
                                            status = "okay";
                                            reg = <0>;
                                            isl79987_csi_in0: endpoint@0 {
                                                    status = "okay";
                                                    port-index = <0>;
                                                    bus-width = <1>;
                                   
                                                    remote-endpoint = <&isl79987_out0>;
                                            };
                                    };
                                    port@1 {
                                            status = "okay";
                                            reg = <1>;
                                            isl79987_csi_out0: endpoint@1 {
                                                    status = "okay";
                                                    remote-endpoint = <&isl79987_vi_in0>;
                                            };
                                    };
                            };
                    };

            }; // end nvcsi
    }; // end host1x

    i2c@3180000
    {
                    isl79987_a@44
                    {
                            status = "okay";          
                            compatible = "isil,isl79987";

                            reg = <0x44>;

                            sensor_model ="isl79987";

                            pix_clk_hz = "27000000";//216Mbps * 1 lnae / 8(bits per pixel)

                            reset-gpios = <&tegra_main_gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
			lane_polarity = "2";

                            ports {
                                    status = "okay";
                                    #address-cells = <1>;
                                    #size-cells = <0>;

                                    port@0
                                    {
                                            status = "okay";
                                            reg = <0>;
                                            isl79987_out0: endpoint
                                            {
                                                    status = "okay";

                                                    data-lanes = <1>;
                                                    bus-width = <1>;
                                                    port-index = <0>;


                                                    clock-lanes = <0>;
                                                    link-frequencies = /bits/ 64 <108000000 216000000 432000000>;

                                                    remote-endpoint = <&isl79987_csi_in0>;
                                            };
                                    };

                                    port@1 {
                                            status="okay";
                                            reg = <1>;
                                    };

                            }; // end ports
                    }; // end isl79987_a
    }; // end i2c

};

/ {

    tegra-camera-platform
    {
            compatible = "nvidia, tegra-camera-platform";
            status = "okay";

            num_csi_lanes = <2>;

            max_lane_speed = <108000000>;
            min_bits_per_pixel = <8>;
            vi_peak_byte_per_pixel = <2>;
            vi_bw_margin_pct = <25>;
            isp_peak_byte_per_pixel = <5>;
            isp_bw_margin_pct = <25>;

            modules {
                    cam_module0: module0
                    {
                            status="okay";

                            badge = "isl79987_rear";
                            position = "rear";

                             orientation = "0";

                            cam_module0_drivernode0: drivernode0
                            {
                                    status="okay";      
                                    pcl_id = "v4l2_sensor";
                                    devname = "isl79987 1-0044";
                                    proc-device-tree = "/proc/device-tree/i2c@3180000/isl79987_a@44";
                            }; // end drivernode0
                    }; // end module0
            }; // end modules
    }; // end tegra-camera-platform

};

This is the trace when catpure is performed using the v4l-ctl command.


Question :
1.Is correct the DT file?
2.why don’t capture work?

Hello and welcome to the NVIDIA Developer forums! I am moving your post to the Jetson forums for visibility.

Cheers,
Tom

hello sandrain00,

since it’s Orin Nano, please aware there’s polarity swap, i.e. CSI0 D1 and CSI1 D0 P/N will always been swizzled for P/N.
you may use device tree property, lane_polarity to configure a polarity swap on any lane.
please also review the schematic for setting this accordingly.
for example,

                                * lane_polarity
                                * Based on the camera connector pin.
                                * CSIx_D0 | CSIx_D1 | CSI(X+1)_D0 | CSI(X+1)CSIx_D1
                                *    LSB  |   BIT1  |     BIT2    |      MSB
                                * if there is a polarity swap on any lane, the bit corrsponding
                                * to the lane should be set
                                * e.g. polarity swap on CSIx_D0 only -> lane_polarity = "1"; 0001
                                * e.g. polarity swap on CSIx_D1 and CSI(X+1)_D0 -> lane_polarity = "6"; 0110

Thanks for your information.

the MIPI part of schematic :
image

We use only the CSI0. so above mentioned lane_polarity is “2”.
Ofcourse i have changed lane_polarity value to “6”, then tested it.
still can not capture.

Thanks
JerryChang

hello sandrain00,

please also give it a try to revise num_csi_lanes = <1>; for tegra-camera-platform, this is the setting for total active CSI lanes.

furthermore,
in order to avoid clock configuration related issue, you may try below commands to boost all the VI/CSI/ISP clocks.

sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate

Thanks for your information.

I have tested it the way you told me.
still can not capture.
trace log :



And i wonder about the port index in orin nano.


Is the port index of orin nano and agx xavier the same?

Thanks.

hello sandrain00,

there’s PHY interrupt, the error code 0x1 means LP sequence error has detected on clock lane.
normally, it should follow by LP11->LP01->LP00->LP11 sequence. it’s more like an issue from camera side.
please see-also developer guide, Property-Value Pairs, you may tune the cil_settletime settings.

yes… they’re using the same port index. but Orin Nano has less CSI lanes.

Thanks for your information.

I have tryed to change the cil_settletime value as you are guide.
I have found here are the two method.
The first is to add “modeX” in DT.
The second is to change Nvidia framework source code.

1.The First method

  • if ‘modeX’ key word add to DT,the kernel will panic.
    I want to found the reason, did not found.

2.The Second method

How can change the cil_settletime?

Thanks.

hello sandrain00,

you may update cil_settletime settings in the device tree.
you could recompile the device tree binary from source.
or, you could disassembler the dtb file into text file for edit. for example, $ dtc -I dtb -O dts -o temp.dts tegra234-xxx.dtb, and then, convert the DTS into a DTB file, $ dtc -I dts -O dtb -o output.dtb temp.dts

for loading new device tree, you should edit /boot/extlinux/extlinux.conf to create a new label, with new FDT entry for loading a new dtb file.

Thanks for your information.

The value of cil_settle times is applied well as written in the previous post.


Do you know which value in which file prints the cil value in a log file?

Thansks.

it is CIL ID, there’re two CILs, such as CILA, CILB for each PHY.

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