Hello:
I am using the Orin AGX Dev Kit with JetPack_6.0 to communicate with a device using uart with HW control. I am using ttyTHS1, available on J30 (40-Pin Expansion Header).
I have tried multiple ways to control the UART and enable HW control flow (My own C code using the TERMIO library, and other serial testers such as minicom or this test code) but I cannot seem able to control the RTS pin. The pin is always low. I attached a logic analyzer to the RX, TX, RTS and CTS pins. I also tried connecting CTS to GND, to always indicate to the HW that it can send information. I am able to see the data in the RX and TX pins correctly, but the RTS pin never changes. In all instances of test, HW control flow is enabled by using the flag CRTSCTS, and verified with stty -a -F /dev/ttyTHS1.
My understanding is that, when using TERMIO with the CRTSCTS enabled, that the RTS pin would go high when transmitting, and low when reading. In my case, the RTS pin is always low, regardless if the UART is transmitting or receiving, with HW control flow enabled. Below is an example of a capture of RX and TX pins working, but no change in RTS.
I would appreciate any help on this matter. If nVidia has any scripts or code that can be used to verify the functionality of the HW control flow on their ttyTHSx devices, that would be a huge help!
We want to validate the HW control flow of the nVidia to see if it can be a good fit for our system, and to better understand if we need to do any modifications. In particular, we want to better understand how the delay between the end of a message being transmitted, and the change in the RTS pin. Our understanding is that this pin should be controlled by the kernel if the flag CRTSCTS is passed as a enabled flag of the serial port setup, which we are doing. And this is controlled on the kernel file serial-tegra.c as function set_rts()
Thank you!