Hi,
Yes. I have the Nvidia Jetson Nano P3450 which I understand is the P3448+P3449 module/carrier board and not a custom Nano board from Waveshare. Only the RS485/CAN board is from Waveshare and plugged into the 40 pin header on the Nano.
Here are the outputs per your requests:
cat /etc/nv_tegra_release
# R32 (release), REVISION: 6.1, GCID: 27863751, BOARD: t210ref, EABI: aarch64, DATE: Mon Jul 26 19:20:30 UTC 2021
cat /etc/nv_boot_control.conf
TNSPEC 3448-400-0000-F.0-1-0-jetson-nano-qspi-sd-mmcblk0p1
COMPATIBLE_SPEC 3448-300-0000--1--jetson-nano-devkit-
TEGRA_CHIPID 0x21
TEGRA_OTA_BOOT_DEVICE /dev/mtdblock0
TEGRA_OTA_GPT_DEVICE /dev/mtdblock0
There are two main approaches I have tried so far. I used jetson-io to enable SPI pins manually per the Waveshare Wiki. This approach seems to enable SPI but not mcp2515.
Some outputs using this approach: Manually configuring SPI pins via Jetson IO:
jetson@nano:~$ dmesg |grep -i spi
[ 0.438236] iommu: Adding device 7000d400.spi to group 7
[ 0.438525] iommu: Adding device 7000d600.spi to group 8
[ 0.438794] iommu: Adding device 70410000.spi to group 9
[ 1.151187] tegra-qspi 70410000.spi: Prod settings list not found
[ 1.152463] qspi_mtd spi32766.0: MX25U3235F (4096 Kbytes)
[ 1.152474] qspi_mtd spi32766.0: mtd .name = spi32766.0, .size = 0x400000 (4MiB) .erasesize = 0x00001000 (4KiB) .numeraseregions = 0
jetson@nano:~$ lsmod |grep -i spi
spidev 13218 0
jetson@nano:~$ lsmod |grep -i mcp
Waveshare also provided a MCP2515 dts file which seems to bring up the MCP2515 driver but it fails to reset. I used the Waveshare provided MCP2515 dts file to bring up the MCP2515 as a " configure for compatible hardware" via jetson-io menu. The MCP2515 driver loads but it fails to enter conf mode after reset.
Here are some outputs using the: jeston-io “configure for compatible hardware” approach
jetson@nano:~$ dmesg |grep -i spi
[ 0.442384] iommu: Adding device 7000d400.spi to group 7
[ 0.442652] iommu: Adding device 7000d600.spi to group 8
[ 0.442915] iommu: Adding device 70410000.spi to group 9
[ 1.145601] tegra-qspi 70410000.spi: Prod settings list not found
[ 1.146836] qspi_mtd spi32766.0: MX25U3235F (4096 Kbytes)
[ 1.146846] qspi_mtd spi32766.0: mtd .name = spi32766.0, .size = 0x400000 (4MiB) .erasesize = 0x00001000 (4KiB) .numeraseregions = 0
[ 5.955028] mcp251x spi0.0: MCP251x didn't enter in conf mode after reset
[ 5.955040] mcp251x spi0.0: Probe failed, err=16
[ 5.955054] mcp251x: probe of spi0.0 failed with error -16
[ 6.999782] mcp251x spi1.0: MCP251x didn't enter in conf mode after reset
[ 7.007515] mcp251x spi1.0: Probe failed, err=16
[ 7.014495] mcp251x: probe of spi1.0 failed with error -16
jetson@nano:~$ lsmod |grep -i spi
spidev 13218 0
jetson@nano:~$ lsmod |grep -i mcp
mcp251x 13742 0
can_dev 13592 1 mcp251x
I have emailed Waveshare because there is something unclear about the dts they provided. The Waveshare Extension board schematics shows that PIN29 of the nano/40 pin header goes to the INT pin of the MCP2515 but the dts file seems to show PIN22 being used instead of pin29.
This is the dts file content Waveshare provided:
// SPDX-License-Identifier: GPL-2.0-only
/*
* Jetson Device-tree overlay for
* MCP2515
*
* Copyright (c) 2020 Seeed Technology Co,Ltd - https://www.seeed.cc.
* All rights reserved.
*
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/pinctrl/tegra210-p3448-0000-p3449-0000-a02.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/gpio/tegra-gpio.h>
/ {
overlay-name = "MCP251x CAN Controller";
compatible = JETSON_COMPATIBLE;
fragment@1{
target-path = "/spi@7000d400/spi@1";
__overlay__ {
status = "okay";
};
};
fragment@4 {
target-path = "/";
__overlay__ {
clocks {
mcp251x_osc: mcp251x_osc {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <8000000>;
clock-accuracy = <100>;
clock-output-names = "mcp251x_osc";
status = "okay";
};
};
};
};
fragment@5 {
target = <&spi0>;
__overlay__ {
/* avoid dtc warning */
#address-cells = <1>;
#size-cells = <0>;
compatible = "nvidia,tegra210-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pinmux>;
nvidia,always-hw-cs;
can0: can@0 {
compatible = "microchip,mcp2515";
status = "okay";
reg = <0x0>; /* spi chip select 0 */
clocks = <&mcp251x_osc>;
interrupt-parent = <&gpio>;
/* GPIO13, HDR PIN22, TEGRA spi2_miso_pb5 */
interrupts = <TEGRA_GPIO(B, 5) IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
};
fragment@10 {
target = <&pinmux>;
__overlay__ {
spi0_pinmux: header-40pin-spi0-pinmux {
**/* can0 /intr */**
** pin22 {**
** nvidia,pins = "spi2_miso_pb5";**
** nvidia,function = "rsvd2";**
** nvidia,pull = <TEGRA_PIN_PULL_UP>;**
** nvidia,tristate = <TEGRA_PIN_DISABLE>;**
** nvidia,enable-input = <TEGRA_PIN_ENABLE>;**
** };**
pin19 {
nvidia,pins = "spi1_mosi_pc0";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin21 {
nvidia,pins = "spi1_miso_pc1";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin23 {
nvidia,pins = "spi1_sck_pc2";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
/* spi0.cs1 */
pin24 {
nvidia,pins = "spi1_cs0_pc3";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
};
};
The kernel pin mapping dts/dtbo reaches the limit of my present knowledge but my suspicion is that if pin 22 is changed to pin 29 the mcp2515 may get past initialization but I am not certain. Not sure where to look on pin mapping registers and settings for the Nano/Linux stuff yet? I would need to learn more about this but hoping for some help so I can dive up into CAN bus and not down into registers :)
Thanks for the help!
Wess
