Jetson Nano SDMMC3 for wifi cannot work after uptime over 30s

We have a custom carrier board that interfaced SDMMC3 with ap6256 Wifi chip, and there is a issue:

Before uptime reached 30s, the *ko files were normally insmoded , then it worked well, and we could ssh to nano through wlan0.

When kernel uptime reached 30s, dmesg output:
then console became blocked.

Certainly, if *ko files were not loaded,the console would not block up.

If the ko files were loaded after kernel uptime reached 30s, the driver could not detect wifi chip. We speculate that this is related to “vdd: disabling” in dmesg.

sdhci@700b0400 { 			/* SDMMC3 for wifi */
		status = "okay"; 
		mmc-ocr-mask = <3>;
		uhs-mask = <0x0>;
		tap-delay = <3>;

Use the uart to debug instead of using ssh for such case.

Ssh is one way to test wifi function for us, we still use uart to debug. Do you need any information?

I just want to know that, did you give any “vmmc-supply” to the sdhci controller?

sdhci needs to use a regulator to control the VDD even when your real power source is always-on.

Yes, the included file "tegra210-porg-power-tree-p3448-0000-a00.dtsi " has following section, it has not been modified by us.

	 sdhci@700b0400 {
                vqmmc-supply = <&max77620_sd3>; /* SDMMC3 for 2nd Wifi on loki */
                vmmc-supply = <&p3448_vdd_3v3_sys>; /* SDMMC3 no stuff for full size SD on foster */

So the power source for your wifi card is 3v3 from the module PMIC?

At the beginning, the measured voltage of SDIO_DATA_CMD was 2.8 V , it fell to 2V when kernel uptime reached 30s.

Generally, if you customize anything, you need to configure the device tree to match the power source as your hardware design…

It is not possible that our default device tree will know your hardware setting.

The power source of wifi chip is not from Nano modules,

We wonder what happend to nano when kernel uptime reached 30s.
Before the 30s , wifi worked well, so the sdhci configuration should be right.
Is there any power save mode on Nano ?

SDIO by default does not have power save. At least we didn’t hear any other users asked this.

Maybe you can check with the vendor.

So I can not understand the section "vdd *:disabling" in dmesg , which module or function could output that.

Those log indicate some regulators are not in use at all so our system disable it.

If you don’t see the regulator name of “p3448_vdd_3v3_sys” and “max77620_sd3” from that disable log, then they are not related to your issue.

If as you have said they were not related ,why did the measured voltage of SDIO_DATA_CMD fall to 2V at the 30s.
How can we stop the “disbling” function?

Please check kernel/kernel-4.9/drivers/regulator/core.c. ->regulator_late_cleanup().

Please notice that the first check in this function is :

if (c && c->always_on) return 0;

Thus, if the device tree you shared with me is true, which means “vqmmc-supply” and “vmmc-supply” are always-on, these two won’t get disabled.

Thank you very much.
We have solved the problem in that way: add “regulator-always-on” in “ vdd-3v3-sd”、“ vddio-sdmmc3-ap”and " vddio-sdmmc-ap" regulator.

Hi @yangchuan ,

I think the real solution should be you need to find out why these 3 regulators affect your case… But not just let them turned on.

They are using default setting as the devkit design. Maybe those GPIO affect your board.

Yes, we should find the reason.