Enabling SDIO on NVIDIA devkit carrier board

Autonomous Machines Jetson & Embedded Systems Jetson Nano
1

I would like to test an m.2 SDIO wifi card on the NVIDIA devkit carrier board. Can anyone confirm which of the sdhci devices in the device tree need to be enabled to test this, what device tree configurations to add, and how to verify it is correctly configured?

I see following potential SDHCI devices:

sdhci@700b0600 /* SDMMC4 for EMMC */
sdhci@700b0400
sdhci@700b0200 /* SDMMC2 for Wifi */
sdhci@700b0000 /* SDMMC1 for SD card */

Would sdhci@700b0400 be the correct port to enable for the m.2 SDIO pins?

At the moment I’m trying to enable sdhci@700b0200 (since a comment mentions SDMMC2 is for wifi), using the following configuration (printout from dtc -I fs …), but I don’t see anything related to sdio appearing in dmesg during bootup.

sdhci@700b0200 {
                cap-mmc-highspeed;
                compatible = "nvidia,tegra210-sdhci";
                clocks = <0x21 0x9 0x21 0xf3 0x21 0xc1>;
                nvidia,runtime-pm-type = <0x1>;
                cap-sd-highspeed;
                resets = <0x21 0x9>;
                cap-sdio-irq;
                clock-names = "sdmmc", "pll_p", "sdmmc_legacy_tm";
                pll_source = "pll_p";
                keep-power-in-suspend;
                nvidia,min-tap-delay = <0x6a>;
                ddr-clk-limit = <0x2719c40>;
                status = "enabled";
                nvidia,max-tap-delay = <0xb9>;
                interrupts = <0x0 0xf 0x4>;
                bus-width = <0x4>;
                phandle = <0x11e>;
                calib-1v8-offsets = <0x505>;
                tap-delay = <0x4>;
                nvidia,en-io-trim-volt;
                force-non-removable-rescan;
                reg = <0x0 0x700b0200 0x0 0x200>;
                default-drive-type = <0x1>;
                mmc-ocr-mask = <0x0>;
                compad-vref-1v8 = <0x7>;
                trim-delay = <0x8>;
                reset-names = "sdhci";
                vmmc-supply = <0x47>;
                linux,phandle = <0x11e>;
                non-removable;
                ignore-pm-notify;
                compad-vref-3v3 = <0x7>;
                calib-3v3-offsets = <0x505>;
                aux-device-name = "sdhci-tegra.1";
                vqmmc-supply = <0x36>;
                max-clk-limit = <0xc28cb00>;

                prod-settings {
                        #prod-cells = <0x3>;

                        prod_c_sdr104 {
                                prod = <0x100 0xff0000 0x40000 0x1c0 0xe000 0x4000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod {
                                prod = <0x100 0x1fff000e 0x8090028 0x1c0 0x8001fc0 0x8000040 0x1c4 0x77 0x0 0x120 0x20001 0x1 0x128 0x43000000 0x0 0x1f0 0x80000 0x80000>;
                        };

                        prod_c_hs {
                                prod = <0x100 0xff0000 0x40000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_sdr50 {
                                prod = <0x100 0xff0000 0x40000 0x1c0 0xe000 0x8000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_ddr52 {
                                prod = <0x100 0x1fff0000 0x40000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_sdr12 {
                                prod = <0x100 0xff0000 0x40000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_ds {
                                prod = <0x100 0xff0000 0x40000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_hs200 {
                                prod = <0x100 0xff0000 0x40000 0x1c0 0xe000 0x4000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_sdr25 {
                                prod = <0x100 0xff0000 0x40000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };

                        prod_c_hs533 {
                                prod = <0x100 0xff0000 0x40000 0x1c0 0xe000 0x2000 0x1e0 0xf 0x7 0x1e4 0x30000505 0x30000505>;
                        };

                        prod_c_hs400 {
                                prod = <0x100 0xff0000 0x40000 0x1c0 0xe000 0x4000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30000505>;
                        };
                };

What can I expect to see when I have correctly configured pins for SDIO? Will there be some printouts in dmesg indicating initialization of some tegra SDIO module?

2

hello phahn,

may I know which wifi module you’re working with?
for example, we had some known issue with Intel-8260, it’ll causing I2C down and thus USB also down.
BTW,
please access Tegra-X1 TRM, and please refer to [Chapter-32 SD/MMC CONTROLLER] for more details.
thanks

3

Hi Jerry,

I’m trying to test a Telit WE866C3-P m.2 card (SDIO only).

Is there any info about configuring the sdhci device tree node for sdio operation or will I need to derive configuration based on TRM and kernel SDHCI driver?

Thanks for the link to the TX1 TRM, it has good information.

4

Actually I think you could refer to TX1 OEM design guide and also corresponding device tree.
As you know jetson nano is also a TX1 chip, this part should be similar.

However, please also refer to Jetson Nano product design guide too. On jetson nano, we only reveal SDMMC3 out. Unlike TX1, which is using SDMMC2.

Also, to know the meaning of each property of device tree, please refer to
kernel/kernel-4.9/Documentation/devicetree/bindings/mmc/sdhci-tegra.txt

5

Hi Wayne,

Thanks for the reply. After enabling sdmmc3 in device tree and MMC debugging in kernel config, I see that SDHCI driver attempts to detect the SDIO device, but so far I’m not having luck. I think it may be related to pin configuration, I’ll be opening a different forum ticket to ask my question.

I tested this chip on the TX1 with the same device tree modifications (except to the file tegra210-p2180-common.dtsi), and see SDIO initialization succeed in boot logs, so I guess I’m just running into boot time pin initialization differences on the Jetson Nano.

This is my current device tree modification:

diff --git a/kernel-dts/tegra210-porg-p3448-common.dtsi b/kernel-dts/tegra210-porg-p3448-common.dtsi
index 7cb5e00..855df17 100644
--- a/kernel-dts/tegra210-porg-p3448-common.dtsi
+++ b/kernel-dts/tegra210-porg-p3448-common.dtsi
@@ -249,10 +249,13 @@
                max-clk-limit = <0xbebc200>;
        };
 
-       sdhci@700b0400 {
-               status = "disabled";
-               /delete-property/ keep-power-in-suspend;
-               /delete-property/ non-removable;
+       sdhci@700b0400 { /* SDMMC3 on m.2 */
+               status = "okay";
+               cap-sdio-irq;
+               non-removable;
+               enable-sdio-wakeup;
+               bus-width = <4>;
+               only-1-8-v;
        };
 
        sdhci@700b0200 { /* SDMMC2 for Wifi */
6

Hi,

I think you could share full dts and dmesg too.

Do you also use sdmmc3 on TX1? How about comparing the sdhci part device tree between tx1 and nano?

7

Hi WayneWWW,

I tested this part on a TX1 with similar device tree modifications and am able to see SDIO enumeration succeed, so I believe there is a difference in m.2 pin initialization causing the enumeration failure. There are a few pins that I need to configure in specific way according to WiFi module spec, can you help identify to which Nano SOM pins these m.2 pins are connected, since the connection is not identified in the reference schematics (Jetson_Nano_Carrier_Board_OrCAD_Schematics.pdf):

Name/Pin number in Jetson_Nano_Carrier_Board_OrCAD_Schematics.pdf
SNN_VENDOR_DEFINED1 - M.2 Key E Pin 42
SNN_VENDOR_DEFINED2 - M.2 Key E Pin 40
SNN_VENDOR_DEFINED3 - M.2 Key E Pin 38
SNN_M2_WIFI_M2_EN - M.2 Key E Pin 23
SNN_M2_WIFI_M2_WAKE_AP - M.2 Key E Pin 21

If you search for these signal names there is no connection to the Nano SOM itself, however using a multimeter I do see at least some of the pins are connected. I just don’t know the pin name since there is no official public pin name listing for the Jetson Nano rev A01 SOM.

Thanks

8

Hi, these SNN pins are float and not connected to module, please just ignore them as they have nothing to do with SDIO port of m.2 device.

9

Hi Trumany,

According on my module datasheet I need to connect M.2 Key E Pin 42 and 40 to 1.8V source for VDDIO. I verified that pins 21 and 23 are connected from the M.2 to the SO-DIMM but as you mention VENDOR_DEFINED pins seem not to be connected through to module, so it looks like this M.2 card cannot work with the Jetson Nano.

Thanks for sharing

10

Hi @phahn,

I have the same module WE866C3 here and Jetson nano A02. Did it work for you?

11

i wasn’t able to get this module to work on any NVIDIA Jetson product. The NVIDIA Jetson nano carrier board is not able to drive the VENDOR_DEFINED pins, so the module will not power up on Jetson Nano systems unless you make a custom carrier board.

The bigger problem however is that the drivers provided for the WE866C3 don’t work with the NVIDIA’s tegra linux release (when testing with the Jetson TX1) Maybe you will have better luck contacting customer support for the WE866C3. Long story short for me, they are not interested in expanding support for this chip outside of the intended target (NXP IMX line of processors)

So far besides the intel wifi chip that come supported out of the box (8265), I’ve found laird st60-2230 (both pcie and sdio version, see SDHCI register being accessed without clock for notes getting sdio working)

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