Hello,
we are having the idea of using the GPIOs of our Jetson Orin Nano to receive Data with a sampling rate of min. 10MHz and a depth of 16bit.
As our application would be quite time-sensitive, we would dedicate one core of the CPU purely for that task - but I am still missing information about the expected min. - max. latency of the GPIOs.
Are there any datasheets available, which contain this information, or does someone maybe have some practical experience of what is realistic?
did you meant the latency of state change when toggle the pin? I don’t have numbers for such use-case, please have a try to evaluate this.
besides, are you using kernel API, or toggling the pin via user-space?
BTW,
you may see-also below commands to adjust the priority (i.e. renice) for camera processes. and, assign CPUs individually (i.e. taskset) for camera application and also test app.
for example, renice
# to modify the priority,
# its ranges from -20 (highest priority) to 19 (lowest priority),
# and, the default is 0.
$ sudo renice -20 -p <pid>
taskset
# to specify CPU-2 and CPU-3 for executing <pid> application.
$ taskset -c -p 2,3 <pid>
thanks a lot for your answer.
The function in question would be a bi-directional bus, based on our own protocol - if we don’t want to add an additional chip, I think only writing a kernel-module for that task would provide the required performance.
Therefore an approximate official magnitude for the latencies of the GPIOs for:
reading the pins values for writing them into a buffer (read)
toggling the values of the pins, from a buffer (write)
…would be important to know, because - dependent on how many pins we use, there would be up to at least 160MBit/s → a sampling rate of 320MHz necessary, which would require a max. latency of 3.125ns (which should not vary…).
We could use 2 pins as well, which would half the required sampling rate .