Jetson Orin NX(JP5.1.2_R35.4.1) mcp2515 can1 can send data, can not recieve data

848145724 · August 28, 2023, 6:06am

Dear all:

1: Orin NX SOM + customed board(p3509), + JP5.1.2, mcp2515 can send data, can not recieve data.
XAVER NX SOM + costomed board(p3509) +JP5.1,2, mcp2515 can send data, can not recieve data.
XAVIER NX SOM + customed board(p3509) + JP4.6, mcp2515 can send data, can recieve data.

In JP4.6,  I change  tegra19x-mb1-pinmux-p3668-a01.cfg as follow.
pinmux.0x0243d040 = 0x00000444; 
pinmux.0x0243d020 = 0x00000444; 
pinmux.0x0243d058 = 0x00000444; 
pinmux.0x0243d010 = 0x00000448; 
--- a/hardware/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
+++ b/hardware/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
@@ -464,12 +466,22 @@
                status = "okay";
        };

+        can_clock: can_clock {
+                 compatible = "fixed-clock";
+                 #clock-cells = <0>;
+                 clock-frequency = <8000000>;
+                 clock-accuracy = <100>;
+        };
+
        spi@3210000{ /* SPI1 in 40 pin conn */
                status = "okay";
                spi@0 { /* chip select 0 */
-                       compatible = "tegra-spidev";
+                       compatible = "microchip,mcp2515";
                        reg = <0x0>;
-                       spi-max-frequency = <50000000>;
+                        spi-max-frequency = <5000000>;
+                        interrupt-parent = <&tegra_main_gpio>;
+                        interrupts = <TEGRA194_MAIN_GPIO(Q, 5) 0x0>;
+                        clocks = <&can_clock>;
                        controller-data {
                                nvidia,enable-hw-based-cs;

2: for Orin NX with JP5.1.2

+++ b/hardware/nvidia/platform/t23x/p3768/kernel-dts/cvb/tegra234-p3509-a02.dtsi
@@ -135,14 +135,26 @@
                nvidia,xusb-padctl = <&xusb_padctl>;
        };

+        can_clock: can_clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <8000000>;
+                clock-accuracy = <100>;
+        };
+
        spi@3210000{ /* SPI1 in 40 pin conn */
                status = "okay";
                spi@0 { /* chip select 0 */
-                       compatible = "tegra-spidev";
+                       compatible = "microchip,mcp2515";
                        reg = <0x0>;
-                       spi-max-frequency = <50000000>;
+                       spi-max-frequency = <200000>;
+                       nvidia,rx-clk-tap-delay = <0x7>;
+                        interrupt-parent = <&tegra_main_gpio>;
+                        interrupts = <TEGRA234_MAIN_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+                        clocks = <&can_clock>;
+                        nvidia,enable-hw-based-cs;
+

 tegra234-mb1-bct-gpioint-p3767-0000.dts       2023-08-17 16:41:32.113385966 +0800
@@ -181,11 +181,6 @@
             pin-0-int-line = <0>; // GPIO Z0 to INT0
             pin-1-int-line = <0>; // GPIO Z1 to INT0
             pin-2-int-line = <0>; // GPIO Z2 to INT0
-            pin-3-int-line = <0>; // GPIO Z3 to INT0
-            pin-4-int-line = <0>; // GPIO Z4 to INT0
-            pin-5-int-line = <0>; // GPIO Z5 to INT0
-            pin-6-int-line = <0>; // GPIO Z6 to INT0
-            pin-7-int-line = <0>; // GPIO Z7 to INT0
         };
 tegra234-mb1-bct-pinmux-p3767-hdmi-a03.dtsi   2023-08-25 16:18:30.619419302 +0800
@@ -731,18 +731,18 @@

                        spi1_sck_pz3 {
                                nvidia,pins = "spi1_sck_pz3";
-                               nvidia,function = "rsvd1";
-                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               nvidia,function = "spi1";
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        spi1_miso_pz4 {
                                nvidia,pins = "spi1_miso_pz4";
-                               nvidia,function = "rsvd1";
-                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                               nvidia,function = "spi1";
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
@@ -751,20 +751,20 @@

                        spi1_mosi_pz5 {
                                nvidia,pins = "spi1_mosi_pz5";
-                               nvidia,function = "rsvd1";
-                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               nvidia,function = "spi1";
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        spi1_cs0_pz6 {
                                nvidia,pins = "spi1_cs0_pz6";
-                               nvidia,function = "rsvd1";
-                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
-                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               nvidia,function = "spi1";
+                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

After insmod mcp251x.ko, but can1 just can send data, can not recieve data.
Thank you very much. Best Regards to all.

KevinFFF · August 28, 2023, 6:43am

Hi 848135724,

Could you share the block diagram of your connection?

Have you verified SPI loopback test before using MCP2515 for CAN communication?

848145724 · August 28, 2023, 7:01am

SPI loopback test wasn`t verified before.I will try.

KevinFFF · August 29, 2023, 5:15am

I would like to know the block diagram of the connections between your board to MCP2515 and the CAN devices.

Yes, please verify SPI loopback test worked before using this module for CAN.

848145724 · August 29, 2023, 7:17am

KevinFFF · August 29, 2023, 8:04am

It seems you didn’t receive the data you sent during SPI loopback test.
Do you short MISO and MOSI of spi1?

Have you confirmed if the Vcc for MCP2515 is 3.3V rather than 5V?

848145724 · August 30, 2023, 8:28am

sudo busybox devmem 0x0243d008 32 0x400
sudo busybox devmem 0x0243d018 32 0x450
sudo busybox devmem 0x0243d028 32 0x400
sudo busybox devmem 0x0243d040 32 0x400

After short MOSI and MISO of spi1, spi1 seem work normal.

and the VCC for mcp2515 is 3.3V.

KevinFFF · August 30, 2023, 8:42am

Let me share the block diagram of my connection and the steps to verify MCP2515 on OrinNX+p3768 devkit.

Connections

Setup

Mapping

SPI:
spi1: spi@3210000
spi3: spi@3230000

Interrupt:
PIN29 → GPIO01 → PQ.05
PIN33 → GPIO13 → PH.00

Steps to verify

Step1. Add configuration in device tree for MCP2515
diff --git a/cvb/tegra234-p3768-0000-a0.dtsi b/cvb/tegra234-p3768-0000-a0.dtsi
--- a/cvb/tegra234-p3768-0000-a0.dtsi
+++ b/cvb/tegra234-p3768-0000-a0.dtsi
@@ -162,12 +162,24 @@
 			};
 		};
 	};
+
+	can_clock: can_clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-accuracy = <100>;
+	};
+
 	spi@3210000{ /* SPI1 in 40 pin conn */
 		status = "okay";
 		spi@0 { /* chip select 0 */
-			compatible = "tegra-spidev";
+			compatible = "microchip,mcp2515";
 			reg = <0x0>;
-			spi-max-frequency = <50000000>;
+			spi-max-frequency = <2000000>;
+			interrupt-parent = <&tegra_main_gpio>;
+			interrupts = <TEGRA234_MAIN_GPIO(Q, 5) IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&can_clock>;
+			nvidia,enable-hw-based-cs;
 			controller-data {
 				nvidia,enable-hw-based-cs;
 				nvidia,rx-clk-tap-delay = <0x10>;
@@ -189,9 +201,13 @@
 	spi@3230000{ /* SPI3 in 40 pin conn */
 		status = "okay";
 		spi@0 { /* chip select 0 */
-			compatible = "tegra-spidev";
+			compatible = "microchip,mcp2515";
 			reg = <0x0>;
-			spi-max-frequency = <50000000>;
+			spi-max-frequency = <2000000>;
+			interrupt-parent = <&tegra_main_gpio>;
+			interrupts = <TEGRA234_MAIN_GPIO(H, 0) IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&can_clock>;
+			nvidia,enable-hw-based-cs;
 			controller-data {

Step2. Configure pinmux for CAN bus through Jetson-IO
2-1 Run Jetson-IO
$ sudo /opt/nvidia/jetson-io/jetson-io.py

2-2 Enable spi1 and spi3
Configure Jetson 40pin Header -> Configure header pins manually -> Enable spi1/spi3 as following -> Back -> Save pin changes -> Save and reboot to reconfigure pins -> Enter
 [*] spi1           (19,21,23,24,26)
 [*] spi3           (13,16,18,22,37)

Step3. Enable can0/can1 and test
$ sudo ip link set can0 up type can bitrate 500000
$ sudo ip link set can1 up type can bitrate 500000
$ candump -x any &
$ cangen can0

KevinFFF · August 30, 2023, 8:48am

Please refer to above steps and the configuration to verify MCP2515 on your board.
Maybe you could try using 5V for MCP2515 module.

Since you are using custom p3509 board so that you should modify the correct dtsi file in Step1. (should be tegra234-p3767-000X-p3509-a02.dts, depending on which Orin NX module you are using)

848145724 · August 30, 2023, 10:30am

after change GPIO_ACTIVE_LOW to IRQ_TYPE_LEVEL_LOW, can work.
Thank you very much.

system · September 25, 2023, 6:25am

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