M.2 Key Type E interface on Jetson TX2

Hi,

I am trying to interface Intel Dual Band Wireless-AC8260(8260NGW) module to Jetson Tx2 development kit. Connected WiFi module to M.2Key Type-E connector(J18) on the development kit. But not seeing WiFi module getting detected or working. Can anyone have solution for this?

I am using Jetpack3.2.1 package on the Tx2 board. Here is the “dmesg” log for pcie.

nvidia@tegra-ubuntu:~ dmesg | grep pci [ 0.142400] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500 [ 0.143112] node /plugin-manager/fragment-500-e3325-pcie match with board >=3310-1000-500 [ 0.267179] iommu: Adding device 10003000.pcie-controller to group 50 [ 7.673500] tegra-pcie 10003000.pcie-controller: 4x1, 1x1 configuration [ 7.683303] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails [ 7.693068] tegra-pcie 10003000.pcie-controller: probing port 0, using 4 lanes [ 7.704583] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes [ 8.150803] tegra-pcie 10003000.pcie-controller: link 0 down, retrying [ 8.560818] tegra-pcie 10003000.pcie-controller: link 0 down, retrying [ 8.970795] tegra-pcie 10003000.pcie-controller: link 0 down, retrying [ 8.972813] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring [ 9.376894] tegra-pcie 10003000.pcie-controller: link 2 down, retrying [ 9.856736] tegra-pcie 10003000.pcie-controller: link 2 down, retrying [ 10.282827] tegra-pcie 10003000.pcie-controller: link 2 down, retrying [ 10.284847] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring [ 10.284854] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected [ 10.285212] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails nvidia@tegra-ubuntu:~ lspci
nvidia@tegra-ubuntu:~$

Thanks.

Please refer to TX2 adaptation guide and this wiki page:
https://elinux.org/Jetson/TX2_USB

Hi Wayne,

I have refereed the adaptation guide as you suggested to interface Intel Dual Band Wireless-AC8260(8260NGW) module to Jetson Tx2 development kit. Connected WiFi module to M.2Key Type-E connector(J18) on the development kit.

  1. set ODMDATA=0x90000 for Configuration #1 in file jetson-tx2.conf

  2. PCIe Interface #2 can be brought to the PEX1 pins on Jetson TX2 depending on
    the setting of a multiplexor on the module. The selection is controlled by QSPI_IO2
    configured as a GPIO

    To switch USB_SS0 to PEX1, configure QSPI_IO2 as follows:
    pcie0_lane2_mux {
    gpio-hog;
    gpios = <TEGRA_MAIN_GPIO(R, 3) 0>;
    output-low;
    label = “pcie-lane2-mux”;
    status = “okay”;
    };

  3. [ 0.142498] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500
    [ 0.142936] node /plugin-manager/fragment-500-xusb-config match with board >=3310-1000-500
    [ 0.143213] node /plugin-manager/fragment-500-e3325-pcie match with board >=3310-1000-500

I have disabled all the above frangment from file tegra186-quill-p3310-1000-a00-plugin-manager.dtsi to avoid any ovelay.

After then i have flash the new dtb. then i checked with lspci command.

root@edgeos:/# dmesg | grep pcie
[ 1.206683] GPIO line 459 (pcie-lane2-mux) hogged as output/low
[ 1.237470] iommu: Adding device 10003000.pcie-controller to group 49
[ 12.411106] tegra-pcie 10003000.pcie-controller: 4x1, 1x1 configuration
[ 12.424572] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[ 12.434237] tegra-pcie 10003000.pcie-controller: probing port 0, using 4 lanes
[ 12.446736] tegra-pcie 10003000.pcie-controller: probing port 1, using 0 lanes
[ 12.456834] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[ 13.005085] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 13.432904] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 13.841091] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[ 13.849096] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[ 14.265082] tegra-pcie 10003000.pcie-controller: link 1 down, retrying
[ 14.705088] tegra-pcie 10003000.pcie-controller: link 1 down, retrying
[ 15.116730] tegra-pcie 10003000.pcie-controller: link 1 down, retrying
[ 15.118743] tegra-pcie 10003000.pcie-controller: link 1 down, ignoring
[ 15.522375] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 15.933371] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 16.343338] tegra-pcie 10003000.pcie-controller: link 2 down, retrying
[ 16.351894] tegra-pcie 10003000.pcie-controller: link 2 down, ignoring
[ 16.358427] tegra-pcie 10003000.pcie-controller: PCIE: no end points detected
[ 16.365734] tegra-pcie 10003000.pcie-controller: PCIE: Disable power rails
root@edgeos:/#

But Still not able to detect 8260nwg wifi-pcie module

ranjit.jambhale,

Sorry that I just checked the whole thread again and find it is weird.

If your case is on Jetson Tx2 development kit, the plugin-manager with “fragment-500-e3325-pcie” would just enable m.2 pcie and there is no need for you to try the method in elinux page.

I also have one wifi chip for m.2 key interface. Let me try it for you first.

ranjit.jambhale,

Just confirmed that if you use 0x90000 in ODMDATA when flashed, the pcie on m.2-key should be enabled.

Log

nvidia@tegra-ubuntu:~$ lspci
00:03.0 PCI bridge: NVIDIA Corporation Device 10e6 (rev a1)
01:00.0 Network controller: Qualcomm Atheros QCA6174 802.11ac Wireless Network Adapter (rev 32)
nvidia@tegra-ubuntu:~$ dmesg | grep pci
[    0.142341] node /plugin-manager/fragment-500-pcie-config match with board >=3310-1000-500
[    0.143051] node /plugin-manager/fragment-500-e3325-pcie match with board >=3310-1000-500
[    0.143068] node /plugin-manager/fragment-500-e3325-pcie match with odm-data enable-pcie-on-uphy-lane0
[    0.263687] GPIO line 459 (pcie-lane2-mux) hogged as output/low
[    0.267109] iommu: Adding device 10003000.pcie-controller to group 50
[    7.593985] tegra-pcie 10003000.pcie-controller: 4x1, 1x1 configuration
[    7.604046] tegra-pcie 10003000.pcie-controller: PCIE: Enable power rails
[    7.614278] tegra-pcie 10003000.pcie-controller: probing port 0, using 4 lanes
[    7.625973] tegra-pcie 10003000.pcie-controller: probing port 2, using 1 lanes
[    8.058618] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    8.479863] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    8.856608] tegra-pcie 10003000.pcie-controller: link 0 down, retrying
[    8.858616] tegra-pcie 10003000.pcie-controller: link 0 down, ignoring
[    8.858913] tegra-pcie 10003000.pcie-controller: PCI host bridge to bus 0000:00
[    8.858917] pci_bus 0000:00: root bus resource [mem 0x50100000-0x57ffffff]
[    8.858919] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff pref]
[    8.858922] pci_bus 0000:00: root bus resource [bus 00-ff]
[    8.858924] pci_bus 0000:00: root bus resource [io  0x1000-0xffff]
[    8.858948] pci 0000:00:03.0: [10de:10e6] type 01 class 0x060400
[    8.859041] pci 0000:00:03.0: PME# supported from D0 D1 D2 D3hot D3cold
[    8.859255] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    8.859378] pci 0000:01:00.0: [168c:003e] type 00 class 0x028000
[    8.859426] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x001fffff 64bit]
[    8.859555] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[    8.859737] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[    8.859766] pci 0000:00:03.0: BAR 8: assigned [mem 0x50200000-0x503fffff]
[    8.859771] pci 0000:01:00.0: BAR 0: assigned [mem 0x50200000-0x503fffff 64bit]
[    8.859786] pci 0000:00:03.0: PCI bridge to [bus 01]
[    8.859792] pci 0000:00:03.0:   bridge window [mem 0x50200000-0x503fffff]
[    8.859857] pcieport 0000:00:03.0: enabling device (0000 -> 0002)
[    8.859933] pcieport 0000:00:03.0: Signaling PME through PCIe PME interrupt
[    8.859935] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt
[    8.859940] pcie_pme 0000:00:03.0:pcie01: service driver pcie_pme loaded
[    8.860012] aer 0000:00:03.0:pcie02: service driver aer loaded

Hi Wayne,

Actually i am adding the required changes in dtb file by converting .dtb file dts then adding changes
and again converting .dts to .dtb file and flash it .

Can you please share me your .dtb file for reference to verify the our changes are correct or not ?

Also i am seeing in my dmesg log
[ 12.411106] tegra-pcie 10003000.pcie-controller: 4x1, 1x1 configuration
Does it conclude that ODMDATA=0x90000 ?

Thanks
Ranjit Jambhale

Hello,

Actually I didn’t modify dtb but just change ODMDATA to 0x90000. Thus, the dtb I am using is just the same from Jetpack.