I am attempting to design a high throughput multi camera system and need to confirm the constraints of the imaging pipeline.
Information I have gathered so far (please correct me if my info is incorrect):
- The Xavier SoC has 16 CSI-2 Lanes. Each lane can handle 2.5Gbps via D-phy
- Each camera group has 4 ports and a camera group can only interface with one type of camera at a time (i.e. 1 to 4 IMX390)
- Each group is connected to 2x Max9296A dual GMSL1/2 Deserializers. Making a total of 8 deserializers available.
- Each deserialize uses 2x CSI-2 lanes per Xavier SoC (really not sure on this one)
- Each deserializer is setup in replication mode to send 2x CSI-2 lanes to each Xavier SoC
- Each deserializers connects via D-Phy and have a max output rate of 2Gbps per lane. Making each deserializer capable of moving 4 Gbps of data (assuming its connected to 2 lanes)
- Therefore each camera group can handle 8Gbps of data.
A. How many Gpps(gigapixels per sec) can the Xavier ICP/ISP process?
B. What is the CSI over head? I can calculate raw bitrate from a camera, but I am assuming there is some overhead.
C. What other aspects/constraints should I be aware of when designing a multi camera suite?
If I take the ARO820 as an example:
8.3Mp * 20fps * 12bit * 4 cameras = 7.96Gbps
That fits within my estimated 8Gbps per camera group but assumes zero overhead. Can the AGX handle 4x AR0820 cameras per camera group? How about 16x AR0820 on 4 camera groups? I imagine I would hit some bottleneck in the image processing pipeline, but I not sure what!