Nvidia agx nx platform about uart driver serial-tegra.c problem

Conditions required to judge the completion of each serial port or delivery process in half-duplex mode.
Judgment criteria related to variables or registers.
I have know
The liunx application layer needs to be provided with the interface to determine the conditions of one receipt or end.
thanks

hello liurui2,

the UART controller supports both 16450 and 16550 compatible modes. default mode is 16450 (non-FIFO mode).
please access Xavier TRM and check page-7994, UART chapter for reference.
thanks

How to distinguish between the hardware uart reg is sent complete

check this, UART_IER_DLAB_0_0. there’s Interrupt Enable for End of Received Data (EORD).

Dear jerry Chang
I still didn’t understand that much.

static struct uart_ops tegra_uart_ops = {
.tx_empty = tegra_uart_tx_empty,
.set_mctrl = tegra_uart_set_mctrl,
.get_mctrl = tegra_uart_get_mctrl,
.stop_tx = tegra_uart_stop_tx,
.start_tx = tegra_uart_start_tx,
.stop_rx = tegra_uart_stop_rx,
.flush_buffer = tegra_uart_flush_buffer,
.enable_ms = tegra_uart_enable_ms,
.break_ctl = tegra_uart_break_ctl,
.startup = tegra_uart_startup,
.shutdown = tegra_uart_shutdown,
.set_termios = tegra_uart_set_termios,
.type = tegra_uart_type,
.request_port = tegra_uart_request_port,
.release_port = tegra_uart_release_port,
};
The linunx application layer needs to send the data to the device through the serial port. The interface logic in the driver is that it can judge the end of one transmission and can start receiving the data.
On the contrary, the logic can be judged after the receiving data

thanks

hello liurui2,

please refer to kernel driver, $L4T_Sources/r32.6.1/Linux_for_Tegra/source/public/kernel/kernel-4.9/drivers/tty/serial/serial-tegra.c
there’s callback function, tegra_uart_tx_dma_complete() to determine the conditions,
thanks