I have ported camera driver from xavier JetPack4.6 to orin JetPack5.0.1. The camera can not preview. V4l2 log is uploaded in the attachment.
Camera sensor work can out put mipi data normally. Status register of camera is OK. So I think some config problem on orin side may result the problem.
Please help analyze the problem
v4l2.txt (3.9 KB)
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I plugged out camera and powered on orin, and run v4l2 command, got the same log as that with camera on above.
Is this problem caused by pinmux? But orin camera pinmux can not be changed.
v4l2-ctl-2300 [003] .... 252.484940: tegra_channel_open: vi-output, imx390 2-001c
v4l2-ctl-2300 [003] .... 252.489636: tegra_channel_set_power: imx390 2-001c : 0x1
v4l2-ctl-2300 [003] .... 252.489645: camera_common_s_power: status : 0x1
v4l2-ctl-2300 [003] .... 252.489652: tegra_channel_set_power: 13e40000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-2300 [003] .... 252.489653: csi_s_power: enable : 0x1
v4l2-ctl-2300 [003] .... 252.490509: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
v4l2-ctl-2300 [005] .... 252.498721: tegra_channel_set_stream: enable : 0x1
kworker/5:1-148 [005] .... 252.501848: rtcpu_string: tstamp:8530998671 id:0x04010000 str:"VM0 activating."
v4l2-ctl-2300 [001] .... 252.508807: tegra_channel_set_stream: 13e40000.host1x:nvcsi@15a00000- : 0x1
v4l2-ctl-2300 [001] .... 252.508809: csi_s_stream: enable : 0x1
v4l2-ctl-2300 [001] .... 252.509096: tegra_channel_set_stream: imx390 2-001c : 0x1
kworker/5:1-148 [005] .... 252.557953: rtcpu_vinotify_event: tstamp:8531623480 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:272997842400 data:0xc55cff0010000000
kworker/5:1-148 [005] .... 252.557954: rtcpu_vinotify_event: tstamp:8531623615 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:272997848992 data:0x0000000031000001
kworker/5:1-148 [005] .... 252.557954: rtcpu_vinotify_event: tstamp:8531623765 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:272997900704 data:0xc55cfc0010000000
kworker/5:1-148 [005] .... 252.557954: rtcpu_vinotify_event: tstamp:8531623896 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:272997907392 data:0x0000000031000002
vi-output, imx3-2302 [011] … 255.199997: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
kworker/5:1-148 [005] … 255.245950: rtcpu_vinotify_event: tstamp:8615610704 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:275699353696 data:0xc55cff0010000000
kworker/5:1-148 [005] … 255.245951: rtcpu_vinotify_event: tstamp:8615610839 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:275699397216 data:0x0000000031000001
kworker/5:1-148 [005] … 255.245951: rtcpu_vinotify_event: tstamp:8615610990 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:275699413248 data:0xc55cfc0010000000
kworker/5:1-148 [005] … 255.245952: rtcpu_vinotify_event: tstamp:8616097008 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:275699599712 data:0x0000000031000002
vi-output, imx3-2302 [001] … 257.759940: tegra_channel_capture_setup: vnc_id 0 W 1920 H 1080 fmt 13
kworker/5:1-148 [005] … 257.765870: rtcpu_vinotify_event: tstamp:8695687861 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:278259324480 data:0xc55cff0010000000
kworker/5:1-148 [005] … 257.765872: rtcpu_vinotify_event: tstamp:8695687998 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:278259363840 data:0x0000000031000001
kworker/5:1-148 [005] … 257.765873: rtcpu_vinotify_event: tstamp:8695688149 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:278259379872 data:0xc55cfc0010000000
kworker/5:1-148 [005] … 257.765873: rtcpu_vinotify_event: tstamp:8695688284 cch:0 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:278259440480 data:0x0000000031000002
(1) our camera hardware is orin+max96712+max9295a.
(2) We have not embedded data along with each frame.
Have reference to below link to check the serdes_pix_clk_hz/pix_clk_hz in device tree.
Hi, ShaneCCC:
(1) serdes_pix_clk_hz
Is this equation that you provide used to calculate serdes_pix_clk_hz in device tree?
if
Output data rate = (sensor or deserializer pixel clock in hertz) * (bits per pixel) / (number of CSI lanes)
Then
serdes_pix_clk_hz = Output data rate * (number of CSI lanes) / (bits per pixel) ,
I use the result of the second equation as serdes_pix_clk_hz in device tree, am I right?
(2) How to caculate pix_clk_hz ?
Yes, check if output data rate > 1.5G for your pix_clk_hz to adjust it to try.
(1)
serdes_pix_clk_hz = Output data rate * (number of CSI lanes) / (bits per pixel) ,
I use the result of the equation as serdes_pix_clk_hz in device tree, am I right?
(2) How to caculate pix_clk_hz ?
(3)our output data rate per lane is 1500Mbps/lane, output data rate = 1.5G,
Hi, ShaneCCC:
(1) I have double checked serdes_pix_clk_hz. The output data rate per lane from deserializer is 1500Mbps, one mipi port has 2 lanes, pixel format is YUV422 8bit, so 1500000000*2/8 = 375000000.
I set serdes_pix_clk_hz = 375000000 in device tree. But the v4l2 log still out put “VIFALC_TDSTATE” only.
(2) Because output data rate per lane from deserializer is equal to1500Mbps, not > 1.5G, I do not care deskew by now.
What should I do next?
The bits per pixel should be 16 for YUV422 format. And you should may the value less than 375000000 to make data rate less than 1.5G instead of equal 1.5G
Hi, ShaneCCC:
The output data rate per lane from deserializer is 1500Mbps， pixel format is YUV422， each PHY has 2 data lanes.
1500000000*2/16 = 187500000 , I configured serdes_pix_clk_hz = 180000000, pix_clk_hz = 180000000
But the output log is still “VIFALC_TDSTATE”
Where is the problem?
Replace the attached binary at …/Linux_for_Tegra/bootloader and have below command to update this debug firmware to collect more information from trace log.
sudo ./flash -r -k A_rce-fw mmcblk0p1 jetson-xxx
camera-rtcpu-t234-rce.img (511.4 KB)
Hi, ShaneCCC:
I have got more detailed log in the attachment file.
Please help.
1.txt (28.3 KB)
Hi,ShaneCCC:
I tested once again, and got the similar log.
Please help to analyze it.
Thanks a lot.
4x2.txt (18.2 KB)
Could you also boost the NVCSI/VI clocks to try.
sudo su
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate
echo 1 > /sys/kernel/debug/bpmp/debug/clk/vi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/isp/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/nvcsi/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
cat /sys/kernel/debug/bpmp/debug/clk/vi/max_rate |tee /sys/kernel/debug/bpmp/debug/clk/vi/rate
832000000
cat /sys/kernel/debug/bpmp/debug/clk/isp/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/isp/rate
1011200000
cat /sys/kernel/debug/bpmp/debug/clk/nvcsi/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/nvcsi/rate
642900000
cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate | tee /sys/kernel/debug/bpmp/debug/clk/emc/rate
3199000000
3.txt (15.9 KB)
The attachment is the new log.
Please help.
Could you try set serdes_pix_clk_hz= 100000000
Hi, ShaneCCC:
When I set serdes_pix_clk_hz= 100000000, the /dev/video0 did not appear after system boot up.
That’s doesn’t make scene for me.
Do you check the kernel message to check why ?
Hi, ShaneCCC:
serdes_pix_clk_hz must be set no less than pix_clk_hz. I set both serdes_pix_clk_hz and pix_clk_hz 100000000. Now program can boot up. But the problem still exists.
4.txt (18.2 KB)