Orin NX use 2 Cameras (both x4 ) issue

[yumi69719]

We have a carrier board with 2 cameras(both x4). Currently, I am facing an issue with using camera0.
My camera0 consists of CSI0_D0 + CSI0_D1 + CSI1_D0 + CSI1_D1 and clock use CSI0_CLK (supported for x4 configuration) , differences from devkit (P3768-A04 Orin Carry Board) CSI1_D0 + CSI1_D1 + CSI0_D0 + CSI0_D1

In design guide Chapter 10 :MIPI CSI VIDEO INPUT, it is said “CSI_0_D1 and CSI_1_D0 have P/N swapped on the module”

my question is how can i config “lane_polarity” is 0 or 6 ?

[ShaneCCC]

Suppose the lane_polarity is 6 for the Orin NX.

Thanks

[yumi69719]

@ShaneCCC

lane_polarity is 6 for the Orin NX.

Yes, I know lane_polarity is 6 for the Orin NX, but my carrier board for MIPI camera 0 is different ‘P3768-A04 Orin Carry Board’. So, is lane_polarity also 6?

" * lane_polarity must be 0x6 for sensors attached to CSI0/1 port, since CSI0 D1 and CSI1 D0 has P/N swizzled, in Orin NX 16GB, Orin NX 8GB, Orin Nano 8GB and Orin Nano 4GB modules. Set it by 0x0 for other cases."

thank you!

[ShaneCCC]

Suppose the pin is swap in the Orin NX module it should need set to 6.

Thanks

[yumi69719]

in the camera0 (CSI0 + CSI1, 4lanes)
i set lane_polarity = “6” and the /dev/video0 can show up , but can’t display image stream normally .

use command is :
“gst-launch-1.0 nvarguscamerasrc sensor-id=0 ! ‘video/x-raw(memory:NVMM),width=(int)1280,height=(int)720,format=(string)NV12,framerate=(fraction)30/1’ ! nvvidconv ! queue ! xvimagesink”

Eventually, an error occurs (pls see attachments).

cam1_gst-launch-1.0.txt (2.1 KB)
cam1_v4l2-ctl.txt (7.8 KB)

my questions are …

1. I want to set the camera0 (CSI0+CSI1) to 4lanes. In addition to using CSI0_CLK (supported for x4 configuration) for the clock and lane_polarity = “6”, which part do I need to modify?
2. What is the definition of serial_a serial_b serial_c serial_d for tegra_sinterface

[ShaneCCC]

I would suggest bring the camera in CSI2+3 4 lanes without lane polarity to make sure the sensor driver then come back to CSI0+1.

Below is the tegra_sinterface map.

CSI0 ↔ serial_a
CSI1 ↔ serial_b
CSI2 ↔ serial_c
CSI3 ↔ serial_d