Hello, i’m relatively new to the Jetson platforms but am exploring some POCs with Orin. My question is whether its possible to bifurcate the x16 slot into several smaller root ports as to interface them with separate end devices. I am not concerned about the single REFCLK from the slot, as the end points I want to interface with will use a single common clock. Does anyone if its possible to bifurcate the PCIe lanes on the Orin dev kit and if so how?
Me too! I think the PCIe plus the GPIO pins make for a lot of possibilities.
I know that they make PCIe splitters, but I suspect the use cases would be pretty specific. We’ve got 16 pins to work with, 8x are gen4, which is the primary reason I went with this unit, how many different ways can you divide them? -I suspect we’ll find out once people start making carrier boards 😅
I’m kind of wondering if it’s worth putting additional acceleration into there -Maybe an A10 would be overkill, maybe not. How are we going to know? But I’m also curious what other options are available.
Sorry for the late response.
We only support the configs listed in the design guide. If one of the configs has PCIe bifurcated it can be supported, if the bifurcation is not listed in the config it is not supported.
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