Jetson AGX Orin , JP5.1.2 and PCIE RP(C5)

[A_Y]

When we use the Jetson AGX Orin Devkit as PCIe x8 (C5,RP) connecting to FPGA(x4, EP), it does not work.
We expected the result that it works because you mentioned below:
“If you want to use a x4 device on x8 configuration, then nothing needs to change. The default software already supported it.”
https://forums.developer.nvidia.com/t/orin-pcie/233122/3

In addition, TRM in Page 7356, “9.3.1.1 Features” says below:
• PCIe controller configurations
x8 lane configuration
Supports x8, x4, x2, and x1 links

However, it works well when we use the Jetson AGX Orin Devkit as PCIe x8 (C5,RP) connecting to FPGA(x8, EP).
Does the PCIe x8 (C5) of the J6 in the Jetson AGX Orin Devkit only support x8 links? Or we need to set up SW?

thanks

[WayneWWW]

You can try to connect other kind of device which also uses x4 configuration to test too but not only FPGA card.

[A_Y]

Thank you for your suggestion.
I will try it but, could you please tell me if the Jetson AGX Orin Devkit as PCIe x8 (C5,RP) support x4 links now?
I believe it supports without SW change.

thanks

[WayneWWW]

I remember that I just randomly plugged a NIC card on Orin Devkit C5 which is not a x8 card and it worked fine.

So, it shall work.

[A_Y]

Thank you for the information. It helps us so much.
I just would like to make sure below:
At that time, you did not change for SW as you mentioned above, right?

thanks

[WayneWWW]

Yes, I didn’t change the lane nums setting.