Is it possible to configure the x16 PCIe port on the Jetson AGX Orin Devkit to run off x2 PCIe lanes instead of the default x8? If so, how do we do this?
No, not possible and no need. x8 is compatible with x2 lane too.
So it is not possible to limit the link width of that port to 2 lanes? This is only for data transfer testing purposes for another piece of hardware that will use that port.
Sorry, not possible.
The developer guide points to the documentation below in reference to configuring link widths.
" For information about Jetson AGX Orin PCIe controller device tree configurations, see the documentation file at:
The
$(KERNEL_TOP)/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txtfile covers topics that include configuring maximum link speed, link width, advertisement of different ASPM states, and so on."
In this I found the following under one of the optional properties listed in the documentation:
- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
improve performance when a platform is designed in such a way that it
satisfies at least one of the following conditions thereby enabling root
port to exchange optimum number of FC (Flow Control) credits with
downstream devices- If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
- If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
a) speed is Gen-2 and MPS is 256B
b) speed is >= Gen-3 with any MPS
The first point highlight that the C5 controller can be run at a x2 link width and the C5 controller is assigned to the PCIe slot. Would configuring the variable at the C5 node change the link width?
One method to try is directly change the num-lanes in device tree from 8 to 2. But I didn’t test this before.
From lower level aspect it is still a x8 but driver side may try x2.
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What are the steps taken to change num-lanes in device tree?
Which steps do you want to know?
Don’t know which files to modify?
Or don’t know how to build devcie tree?
Or don’t know hot do update device tree?
Or don’t know everything above?
Hi,
Can I please receive the documentation or information for all above? This includes the file to modify the num-lanes variable, building device tree and updating device tree.
To provide some background, I’m currently working with the AGX Orin 32GB Developer Kit.
I have come across these links in regards to downloading the source code, building a device tree and flashing a specific partition. Do they answer the above?
Hi,
The source code hardware/nvidia/soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi will have the num-lanes parameters.
The document link you shared is not for Orin. Always ask yourself which jetpack release you are using and whether the document you are reading is matching this version…
https://docs.nvidia.com/jetson/archives/r35.5.0/DeveloperGuide/index.html
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