Jetson AGX Orin - Configuration #2 setting for PCIe interface

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
1

Hi,
We have designed our custom board referring Jetson AGX Orin devkit and design guide and need to configure the UPHY in configuration #2 to make the PCIe interfaces to work. see our required interface mapping in below picture.

Capture-1
Capture-11678×629 210 KB

I have made changes as below in p3767.conf.common file for ODMDATA :

ODMDATA="gbe-uphy-config-0,hsstp-lane-map-3,hsio-uphy-config-16,nvhs-uphy-config-0";

I am not clear on how this is called as config #2

Can you please let me know if this is correct or anything went wrong or missing?
Also do I need to make any change in the source or SOC or pinmux for this?

2

Hi,

Are you asking an issue on Orin AGX or Orin Nano/NX
?

Also, I don’t see any picture you shared


3

Hi,
Sorry, can you see the image now in the original post? I am asking this in Orin AGX

4

Yes, I can see the picture now.

p3767.conf.common is for Orin NX/Nano
 P3701 is for Orin AGX.

1 Like
5

Oh Ok, so this change is correct?
ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,hsio-uphy-config-16,nvhs-uphy-config-0”;

How to know if it is config#2?
on what basis this is named? I could not get the index config-0,map-3, config-16 here. referred the Configuring the UPHY Lane in board bring up guide but could not figure it out.

6

How to know if it is config#2?

You can read the adaptation guide


https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=uphy#uphy-lane-configuration

on what basis this is named? I could not get the index config-0,map-3, config-16 here. referred the Configuring the UPHY Lane in board bring up guide but could not figure it out.

Your hardware guy who designed this board would know. If they don’t even know, then please check the Orin AGX product design guide


Config #2 has nothing to do with those numbers which you don’t understand.

1 Like
7

Hi,

I changed as below for config#2 as per design guide selection. Now my board is not booting after flash. can you suggest ?

ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,nvhs-uphy-config-1,hsio-uphy-config-16,gbe0-enable-10g”;

8

Try to share the UART log during boot
 We are not all-knowing person. I don’t know you and your board. Not able to tell what is missing by just few words here.

9

Also, I don’t know what goes wrong with you.

The document didn’t ask you to use "ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,nvhs-uphy-config-1,hsio-uphy-config-16,gbe0-enable-10g”;

gbe0-enable-10g shall not be here.

nvhs-uphy-config-1 is wrong too.

Please try to clarify what is the exact thing you want to enable on your board.

10

any reason for this?

11

please try to clarify what do you want to enable on your board first. Otherwise I don’t have any answer to you.

What I/Os are needed?

12

Hi,

My requirement is,
UPHY0 → PCIe x1 (C0), RP
USB 3.2 (P1)
USB 3.2 (P2)
PCIe x1 (C1), RP
PCIe x4 (C4), RP

UPHY1 → PCIe x8 (C5), RP/EP

UPHY2 → PCIe x8 (C7), RP/EP

So tried these combinations:
hsstp-lane-map-3,
hsio-uphy-config-16
nvhs-uphy-config-0
gbe-uphy-config-0

changed gbe-uphy-config from 22 to 0 as I am not using MGBE
removed gbe0-enable-10g

So,
ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,nvhs-uphy-config-0,hsio-uphy-config-16”;

Is this OK? But with this change, my PCIe devices are not getting detected

14

I already said this many times. You need to at least share kernel log or boot up log to us to check issue


Also, you need to at least tell other people about which PCIe cannot work
 You have PCIe C1,C4,C5,C7
 which one do you have problem?

15

In configuratin#2 → PCIe x1 (C0), RP and PCIe x8 (C7), RP/EP are not working.

Attached the dmesg log
agx_orin_gigr_dmesg_log (77.8 KB)

16

Hi,

Please read the document here. Besides the ODMDATA, device tree change is also needed.

Default setting does not enable C0 and C7 but only C1,C4,C5.

https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=pcie#enable-pcie-in-a-customer-cvb-design

17

OK let me check on this

18

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