To support Orin NX miniPCI pinmux issue

Hi Team,

I configured in “Jetson_Orin_NX_Series_+HDMI A01” in “Jetson_Orin_NX_series_and_Orin_Nano_series_Pinmux_Config_Template” excel sheet as below.
PEX9_RX0P to PCIe 3 Receive 0+ (PCIe Ctrl #9 Lane 0 .

|60|CSI4_D1_P|PCIE2_RX1_P (PCIE3_RX0_P)||x|PEX9_RX0P|
|58|CSI4_D1_N|PCIE2_RX1_N (PCIE3_RX0_N)||x|PEX9_RX0N|
|66|CSI4_D3_P|PCIE2_TX1_P (PCIE3_TX0_P)||x|PEX9_TX0P|
|64|CSI4_D3_N|PCIE2_TX1_N (PCIE3_TX0_N)||x|PEX9_TX0N|

  1. I changed this configuration, it is not affecting at generated DT file. Generated file is same default generated file.
  2. do i need enable PCIe3 ? If yes can you share the file name and location ?

Please refer to the l4t developer guide document to enable C9. The pinmux does not need change.

1 Like

Hi @WayneWWW ,
My configuration as listed here.
modified “nvidia/platform/t23x/p3768/kernel-dts/cvb/tegra234-p3768-0000-a0-pcie.dtsi” file as below.

    pcie@141e0000 {
            /* C7x1 node */
            status = "okay";
            phys = <&p2u_gbe_0>;
            phy-names = "p2u-0";


    pcie@140a0000 {/* C8 - Ethernet */
            status = "okay";

            nvidia,pex-wake-gpios = <&tegra_main_gpio TEGRA234_MAIN_GPIO(L, 2) GPIO_ACTIVE_LOW>;
    pcie@140c0000 { /* C9x1 */
            status = "okay";
            phys = <&p2u_gbe_1>;
            phy-names = "p2u-0";


  1. C7 configured in “nvidia/soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi”
    /* C7 X8*/
    pcie_c7_rp: pcie@141e0000 {
    compatible = “nvidia,tegra234-pcie”, “snps,dw-pcie”;
    power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
    reg = <0x00 0x141e0000 0x0 0x00020000 /* appl registers (128K) /
    0x00 0x3e000000 0x0 0x00040000 /
    configuration space (256K) /
    0x00 0x3e040000 0x0 0x00040000 /
    iATU_DMA reg space (256K) /
    0x00 0x3e080000 0x0 0x00040000 /
    DBI reg space (256K) /
    0x32 0x30000000 0x0 0x10000000>; /
    ECAM (256MB) */
    reg-names = “appl”, “config”, “atu_dma”, “dbi”, “ecam”;

            status = "okay"; /* disabled*/
            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            num-lanes = <1>; /* 8 */
            num-viewport = <8>;
            linux,pci-domain = <7>;
  2. C9 configured in “nvidia/soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi”
    /* C9 X2 /
    pcie_c9_rp: pcie@140c0000 {
    compatible = “nvidia,tegra234-pcie”, “snps,dw-pcie”;
    power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
    reg = <0x00 0x140c0000 0x0 0x00020000 /
    appl registers (128K) /
    0x00 0x2c000000 0x0 0x00040000 /
    configuration space (256K) /
    0x00 0x2c040000 0x0 0x00040000 /
    iATU_DMA reg space (256K) /
    0x00 0x2c080000 0x0 0x00040000 /
    DBI reg space (256K) /
    0x38 0x30000000 0x0 0x10000000>; /
    ECAM (256MB) */
    reg-names = “appl”, “config”, “atu_dma”, “dbi”, “ecam”;

           status = "okay"; /* disabled */
           #address-cells = <3>;
           #size-cells = <2>;
           device_type = "pci";
           num-lanes = <1>;/* 2 */
           num-viewport = <8>;
           linux,pci-domain = <9>;
  3. modified ODMDATA in p3767.conf.common as below.

CMDLINE_ADD=“mminit_loglevel=4 console=ttyTCU0,115200 console=ttyAMA0,115200 firmware_class.path=/etc/firmware fbcon=map:0 net.ifnames=0”
5) uphy value
nvidia@nvidia-desktop:~$ sudo cat /sys/kernel/debug/bpmp/debug/uphy/config
[sudo] password for nvidia:
6) DTS file attached

With above configuration only M2E key is working. Now question is do i need to change in pinmux ? or any configuration need to change ?

I want use C7 for M2E key and C9 for miniPCI.
3example.dts (430.1 KB)

please clean up your format. It is hard to read your comment.

Also, I don’t know why you need to modify tegra234-soc-pcie.dtsi. Looks not needed.

sorry for lengthy message. total 6 point are there. Each one has configuration info.
shall i revert tegra234-soc-pcie.dtsi modification?

You don’t need to modify the tegra234-soc-pcie.dtsi. Modifying tegra234-p3768-0000-a0-pcie.dts will take same effect.

Without that file i tried did not work. So modified that also. But i compared both generated DTS it was same only. Yes no impact.

Now what you suspect any pin modification or clock enable required?

What is your method to update the device tree?

Where is your dmesg?

I edit the source file manually. And then build , then copy dtb file in /kernel/dtb under L4T
C9pci_dmesg1_logs.txt (17.6 KB)

please try to have some sense of sharing logs… I need the log since the boot starts…

And then build , then copy dtb file in /kernel/dtb under L4T

And then?


  1. next steps are for flashing.
    cd $L4T_DIR
    sudo ./
    sudo ./tools/
    sudo ./tools/kernel_flash/ --external-device nvme0n1p1 -c tools/kernel_flash/flash_l4t_external.xml -p “-c bootloader/t186ref/cfg/flash_t234_qspi.xml” --showlogs --network usb0 jetson-orin-nano-devkit internal

dmesg logs attached
C9pci_dmesg2_logs.txt (73.3 KB)

please convert back the bpmp dtb in your Linux_for_Tegra/bootloader and check the uphy setting too.

uphy {
	status = "okay";
	hsio-uphy-config = <0x00>;
	hsstp-lane-map = <0x03>;
	gbe-uphy-config = <0x08>;

tegra234-bpmp-3767-0001-3509-a02.dts (216.0 KB)

@WayneWWW any thing i might have missed ?

One Observations “tegra194-pcie 140c0000.pcie: Phy link never came up” this is observed in dmesg logs.

Hi @WayneWWW
My shared uphy value is correct? if not what it should be ?
Do you need any more info to get clarity on issue ?

Sorry, it seems ODMDATA is not set correctly.

gbe-uphy-config = <0x08>;

Please check if this patch exists in your file.

You mean to say it should be 0x08 ? Current config file
"ODMDATA=“gbe-uphy-config-9,hsstp-lane-map-3,hsio-uphy-config-0”; " in p3767.conf.common file.

If should be 0x9 but your result shows 0x8.