How to modify the pinmux reuse in Orin nano board, compile it into an image and burn it into the Orin nano development board?

Here is my core board version:

Software part of jetson-stats 4.2.12 - (c) 2024, Raffaello Bonghi
Model: NVIDIA Orin Nano Developer Kit - Jetpack 5.1.3 [L4T 35.5.0]
NV Power Mode[0]: 10W
Serial Number: [XXX Show with: jetson_release -s XXX]
Hardware:
 - P-Number: p3767-0004
 - Module: NVIDIA Jetson Orin Nano (4GB ram)

we designed a develop board and use Orin nano 4G module. We added peripherals to modify the use of pin, changed PCIe X2 (C7) to PCIe X1 (C7) and PCIe X1 (C9), and then modified the enabling C9 according to NVIDIA official documents, but C9 was not enabled。

root@nvidia-desktop:~# lspci
0001:00:00.0 PCI bridge: NVIDIA Corporation Device 229e (rev a1)
0001:01:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8822CE 802.11ac PCIe Wireless Network Adapter
0004:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0004:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation Device 5013 (rev 01)
0008:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0008:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)

I modified the “ODMDATA” in the file p3767.conf.common :

ODMDATA="gbe-uphy-config-9,hsstp-lane-map-3,hsio-uphy-config-0";

It`s still not work. How should I do?

Do you want to dynamically update pinmux or you want to modify it in file and flash it to the board…?

Or you don’t know what I am asking here?

Hi:
The first step is to modify pinmux dynamically, so that we can quickly verify whether our hardware design is correct;
After verifying that the hardware is normal, I need to modify the device tree file to generate firmware.
I think if NVIDIA’s documents were better and more reasonable, people like me who first came into contact with Jetson devices would not ask such simple questions here. There is no need to ask for help on other embedded platforms I have been in contact with.

1 Like

In documents: Jetson Orin NX and Nano Series — NVIDIA Jetson Linux Developer Guide 1 documentation


The description in the document “Do not edit this variable directly in the p3767.conf.common file. You should instead append that variable in your flash configuration file to override the default.”,
Which flash configuration file should I modify?

To modify the pinmux reuse in the Orin Nano board, you’ll need to edit the pinmux configurations in the device tree source files, typically found in the arch/arm64/boot/dts/nvidia/ directory. After making your changes, recompile the device tree and rebuild the kernel and boot image. Once compiled, use the appropriate tools like Jetson-Download or dd to flash the new image onto your board. Make sure to test the changes carefully to ensure everything works as expected.

Jetson’s process doesn’t look like this。
Viewing the Nvidia documentation should be to modify ODMDATA, but it cannot be directly modified to the configuration file. I don’t know where to make the modifications?

請問你現在要問什麼問題?

看起來你改過第一則comment的內容, 已經跟原本的題目完全無關了

Hi WayneWWW:
我们自己设计的硬件因为要添加一个Pcie外设,所以需要设置复用PCIe X1 (C7) 和 PCIe X1 (C9),JetPack中的默认设定也是PCIe x2(C7)的,所以我想将默认的PCIe x2(C7)修改成PCIe X1 (C7) 和 PCIe X1 (C9)。


我查看nvidia的官方文档,是需要设置ODMDATA,但是文档中说明不能修改 p3767.conf.common文件,然后我又去论坛查找: Orin NX 8GB C9 can not get PCIe #C7/#C9 - Jetson & Embedded Systems / Jetson Orin NX - NVIDIA Developer Forums
看到你的回复是不能用原本的dtb,需要使能C7和C9,但是我们不明白怎么使能,我使用的jetson版本:

Software part of jetson-stats 4.2.12 - (c) 2024, Raffaello Bonghi
Model: NVIDIA Orin Nano Developer Kit - Jetpack 5.1.3 [L4T 35.5.0]
NV Power Mode[0]: 10W
Serial Number: [XXX Show with: jetson_release -s XXX]
Hardware:
 - P-Number: p3767-0004
 - Module: NVIDIA Jetson Orin Nano (4GB ram)

我不知道怎么使能C7和C9,所以希望能得到指导,非常感谢。

其實你直接改 p3767.conf.common就可以了. 文件上講的事情是 "理想上"你應該要自己建一個屬於你們自己的board config. 而不是沿用我們的
但如果你不做這件事情也沒有影響.

請問你有改device tree的經驗嗎? 比方說如果連基本概念都沒有,直接教你改C7 /C9就還太早了

如果你知道device tree怎麼運作, 那你貼的那篇其實就已經教你怎麼開C7/C9了

Hi,WayneWWW:
我开始发帖求助前,就是按照其他论坛上说的修改 p3767.conf.common的ODMDATA=“gbe-uphy-config-9,hsstp-lane-map-3,hsio-uphy-config-0”;
修改完以后,我用flash.sh脚本重新烧录到硬件单板上,结果硬件直接异常,无法正常启动,我又改回来了重新烧录就能正常启动了。
我的烧录命令:

./flash.sh jetson-orin-nano-devkit-nvme internal

如果可以直接修改p3767.conf.common,那是不是还有其他文件也需要一起改呢?我只改了这个文件会导致设备异常不启动。
这是我第一次接触jetson的硬件,确实还没有修改过nvidia嵌入式平台的device tree的经验,不过我以前修改过hisi/novatek/Rockchip等嵌入式设备的device tree,这些平台我只需要对照着文档就能明白怎么修改device tree,然后编译device tree,最后烧录device tree,nvidia的我看完文档以后确实不知道该怎么做才是对的。

Hi, WayneWWW:
我觉得我的主要困惑是不知道应该修改哪个文件,我在对照nvidia文档查看的时候,找到一个dtsi文件:
Linux_for_Tegra/source/public/hardware/nvidia/platform/t23x/p3768/kernel-dts/cvb/egra234-p3768-0000-a0-pcie.dtsi
在这个文件中有pcie的配置:

pcie@141e0000 {
		/*
		 * C7 - M2 Key M, default config, other config possible as
		 * below:
		 * C7 x2 - default
		 * C7 x1 or C9 x1
		 */
		status = "okay";
		phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
		phy-names = "p2u-0", "p2u-1";
	};

我可以直接将这个文件中的内存修改为:

        pcie@141e0000 {
		/*
		 * C7 x1
		 */
		status = "okay";
		phys = <&p2u_gbe_0>;
		phy-names = "p2u-0";
		num-lanes = <0x01>;
	};
	pcie@140c0000 {
		/*
		 * C9 x1
		 */
		status = "okay";
		phys = <&p2u_gbe_1>;
		phy-names = "p2u-0";
		num-lanes = <0x01>;
	};

是否这样的改动是有效的?
同级目录下还有tegra234-p3509-a02.dtsi文件,我不确认是哪个文件在生效?
在查找num-lanes的设置的时候,找到Linux_for_Tegra/source/public/hardware/nvidia/soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi文件有这个参数:

/* C9 X2 */
	pcie_c9_rp: pcie@140c0000 {
		compatible = "nvidia,tegra234-pcie", "snps,dw-pcie";
		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
		reg = <0x00 0x140c0000 0x0 0x00020000   /* appl registers (128K)      */
		       0x00 0x2c000000 0x0 0x00040000   /* configuration space (256K) */
		       0x00 0x2c040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
		       0x00 0x2c080000 0x0 0x00040000   /* DBI reg space (256K)       */
		       0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
		reg-names = "appl", "config", "atu_dma", "dbi", "ecam";

		status = "disabled";

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		num-lanes = <2>;
		num-viewport = <8>;
		linux,pci-domain = <9>;

		clocks = <&bpmp_clks TEGRA234_CLK_PEX2_C9_CORE>,
			 <&bpmp_clks TEGRA234_CLK_PEX2_C9_CORE_M>;
		clock-names = "core", "core_m";

		resets = <&bpmp_resets TEGRA234_RESET_PEX2_CORE_9_APB>,
			 <&bpmp_resets TEGRA234_RESET_PEX2_CORE_9>;
		reset-names = "apb", "core";

		interrupts = <0 358 0x04>,	/* controller interrupt */
			     <0 359 0x04>;	/* MSI interrupt */
		interrupt-names = "intr", "msi";

		interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR>,
			        <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW>;
		interconnect-names = "dma-mem", "dma-mem";
		iommus = <&smmu_niso0 TEGRA_SID_NISO0_PCIE9>;
		iommu-map = <0x0 &smmu_niso0 TEGRA_SID_NISO0_PCIE9 0x1000>;
		msi-parent = <&gic_v2m TEGRA_SID_NISO0_PCIE9>;
		msi-map = <0x0 &gic_v2m TEGRA_SID_NISO0_PCIE9 0x1000>;
		dma-coherent;
		iommu-map-mask = <0x0>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &intc 0 358 0x04>;

		nvidia,dvfs-tbl = < 204000000 204000000 665600000  1600000000
				    204000000 665600000 1600000000 2133000000
				    0         0         0          0
				    0         0         0          0 >;

		nvidia,max-speed = <4>;
		nvidia,disable-aspm-states = <0xf>;
		nvidia,controller-id = <&bpmp 0x9>;
		nvidia,tsa-config = <0x0200b004>;
		nvidia,disable-l1-cpm;
		nvidia,aux-clk-freq = <0x13>;
		nvidia,preset-init = <0x5>;
		nvidia,aspm-cmrt = <0x3C>;
		nvidia,aspm-pwr-on-t = <0x14>;
		nvidia,aspm-l0s-entrance-latency = <0x3>;
		nvidia,bpmp = <&bpmp 9>;
		nvidia,aspm-cmrt-us = <60>;
		nvidia,aspm-pwr-on-t-us = <20>;
		nvidia,aspm-l0s-entrance-latency-us = <3>;

		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x00 0x2c100000 0x00 0x2c100000 0x0 0x00100000      /* downstream I/O (1MB) */
			  0x82000000 0x00 0x40000000 0x38 0x28000000 0x0 0x08000000      /* non-prefetchable memory (128MB) */
			  0xc3000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>;    /* prefetchable memory (11904MB) */

		nvidia,cfg-link-cap-l1sub = <0x1b0>;
		nvidia,cap-pl16g-status = <0x174>;
		nvidia,cap-pl16g-cap-off = <0x188>;
		nvidia,event-cntr-ctrl = <0x1c4>;
		nvidia,event-cntr-data = <0x1c8>;
		nvidia,dl-feature-cap = <0x2f8>;
		nvidia,ptm-cap-off = <0x304>;
	};

这个文件应该修改status=“okay”,并且修改num-lanes=<1>;吗?

聽起來你對於device tree的規則好像還不是太熟…

基本上你改tegra234-p3768-0000-a0-pcie.dtsi裡面的status改成okay之後他就會是okay了. 不用回去tegra234-soc-pcie.dtsi改.

這是device tree本來的語法. 跟有沒有用我們的code比較沒有關聯.

我們的DT資料夾檔案擺放的邏輯如下.

/source/public/hardware/nvidia/soc/

soc底下的device tree是通用的. 只要使用相同soc, 這部份就會是共同的code. 比方說t23x soc就是所有Orin系列 (AGX/NX/Nano).

source/public/hardware/nvidia/platform/

platform底下是針對各個平台寫的device tree. 比方說t23x/p3768就是Orin NX/Nano平台. t23x/concord就是Orin AGX. 因為他們都是Orin t23x SOC, 所以他們都會包含上面 soc/t23x底下所有的device tree.

這裡的邏輯就是, 如果你只要改Orin Nano的部份, 那麼你在p3768底下改動就可以了.
比方說我要把c9打開, 我就在p3768底下的device tree把c9的stauts設成okay.

如果你跑回soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi底下開c9 status, 那就會變成你連其他跟Orin nano無關的平台也把C9打開… 因為這部份是所有t23x SOC都通用的

Hi,WayneWWW:
对device tree我确实学习的不多,一般需要改的时候我按照文档改完后就不需要再处理了。
感谢您对nvidia目录结构的解释,我现在修改下Tegra234-p3768-0000-a0-pcie.dtsi,然后编译试试,我想请教下,现在我修改完以后,是需要全部烧录一次呢?还是可以只针对修改的分区进行单独烧录,如果修改后,我可以只针对dtb分区进行烧录就会生效,那样就不用全烧录一次了(全部烧录一次会导致安装在上面的工具,环境和应用全部丢失)。如果可以只烧录修改dtsi影响的分区,我应该烧录哪些分区呢?

如果只是為了目前debug使用, 你可以把build出來的dtb放進 Jeston上的/boot/dtb然後蓋掉原本的檔案.

重開機之後應該就會生效. 有生效的話 dmesg |grep dts前後幾行的內容應該會有所改變 (比方說dts的build time)

如果是以後要整機重燒, 可以把新的dtb放進Linux_for_Tegra/kernel/dtb (host上的路徑)之後做燒錄

Hi,WayneWWW:
我将重新编译出来的dtb文件替换到硬件上的/boot/dtb目录,重启后适用lspci命令查看,还是没有看到使能C9,我具体描述下我的修改流程:
1.修改 p3767.conf.common文件中的ODMDATA

ODMDATA=“gbe-uphy-config-9,hsstp-lane-map-3,hsio-uphy-config-0”;

修改Linux_for_Tegra/source/public/hardware/nvidia/platform/t23x/p3768/kernel-dts/cvb/egra234-p3768-0000-a0-pcie.dtsi文件中的pcie配置,将

    pcie@141e0000 {
		/*
		 * C7 - M2 Key M, default config, other config possible as
		 * below:
		 * C7 x2 - default
		 * C7 x1 or C9 x1
		 */
		status = "okay";
		phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
		phy-names = "p2u-0", "p2u-1";
	};

替换为:

    pcie@141e0000 {
		/*
		 * C7 x1
		 */
		status = "okay";
		phys = <&p2u_gbe_0>;
		phy-names = "p2u-0";
		num-lanes = <0x01>;
	};
	pcie@140c0000 {
		/*
		 * C9 x1
		 */
		status = "okay";
		phys = <&p2u_gbe_1>;
		phy-names = "p2u-0";
		num-lanes = <0x01>;
	};

2.编译kernel,我执行./nvbuild.sh -o $PWD/kernel_out将kernel重新编译一次
3.查看orin nano开发板的/boot/dtb目录下dtb文件名为:kernel_tegra234-p3767-0004-p3768-0000-a0.dtb
4.查看编译的Linux_for_Tegra/source/public/kernel_out/arch/arm64/boot/dts/nvidia目录下所有dtb文件,将其中的tegra234-p3767-0003-p3768-0000-a0.dtb文件拷贝到设备/boot/dtb目录下,并重命名为kernel_tegra234-p3767-0004-p3768-0000-a0.dtb,重启设备。
5.使用命令查看:

root@nvidia-desktop:/boot/dtb# lspci
0001:00:00.0 PCI bridge: NVIDIA Corporation Device 229e (rev a1)
0001:01:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8822CE 802.11ac PCIe Wireless Network Adapter
0004:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0004:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation Device 5013 (rev 01)
0008:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0008:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)
root@nvidia-desktop:/boot/dtb# dmesg | grep "dts"
[    0.002369] DTS File Name: /home/yan/nvidia/nvidia_sdk/JetPack_5.1.3_Linux_JETSON_ORIN_NANO_TARGETS/Linux_for_Tegra/source/public/kernel/kernel-5.10/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t23x/p3768/kernel-dts/tegra234-p3767-0004-p3768-0000-a0.dts
[    2.136350] tegra-pmc c360000.pmc: scratch reg offset dts data not present

从lspci上没有看到C9被使能,这里面我有那一步没有做对吗?

  1. 如果本來系統上用的是 p3767-0004-p3768-0000-a0.dtb 那你應該也要copy對應的0004那一份. 而不是0003.

  2. 能請你分享一下/boot/extlinux/extlinux.conf的內容還有你全部的dmesg嗎?

Hi,WayneWWW:
抱歉,上面的回复是我输入错误,实际上我拷贝的就是tegra234-p3767-0004-p3768-0000-a0.dtb文件,
dmesg.log (90.1 KB)
这个文件中包含/boot/extlinux/extlinux.conf以及dmesg信息。

Hi,

能請你確認一下開機目前這個狀況下的ODMDATA結果嗎?

sudo cat /sys/kernel/debug/bpmp/debug/uphy/config

Hi,WayneWWW:
查询UPHY配置:

root@nvidia-desktop:~# cat /sys/kernel/debug/bpmp/debug/uphy/config 
0x03a00000

从这个配置上看仍然是gbe-uphy-config-8,现在我在p3767.conf.common里面修改了ODMDATA,然后编译替换了tegra234-p3767-0004-p3768-0000-a0.dtb文件,那还有什么文件也替换掉让修改的ODMDATA生效吗?
源码处的配置文件:
tegra234-p3768-0000-a0-pcie.dtsi.txt (1.6 KB)
p3767.conf.common.txt (8.0 KB)