NVME external drive not recognized with AGX Orin SoMs

This is a continuation of a previous post.
To recap, I am trying to get my Orin SoMs to recognize an external NVME 980 GB drive and it is set up as PCIe Controller C0. I believe my pinmux is correct.

My ODMDATA (below) is set for UPHY Configuration #2.
https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#uphy-lane-configuration

ODMDATA=“gbe-uphy-config-0,nvhs-uphy-config-1,hsio-uphy-config-16,hsstp-lane-map-3”;

I changed the appropriate files from the Developers Guide here:

https://docs.nvidia.com/jetson/archives/r35.2.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#enable-pcie-in-a-customer-cvb-design

I changed the code for PCIe x1 (C0) and PCIe x8 (C7) in the files: tegra234-p3737-pcie.dtsi, tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi, & tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi. I recompiled the kernel, copies files over, and flashed.

After booting without issue and logging into the SoM, running the lsblk command does not show the NVME drive present.

We have a similar setup with JetPack 5.1.2 using the Xavier AGX SoMs and it reconignes the NVME drive correctly. Our ODMDATA setting for the Xavier is (fewer parameters compared to the Orin for ODMDATA):

ODMDATA=0x09191000

The GPUs need to be in Endpoint Mode as well (thus why C5 is set to ‘nvhs-uphy-config-1’ for the Orin and 0x09191000 for the Xavier).

I have attached my configuration file used for flashing (I added a .txt extension to the file so I am able to upload here).
auto2-gpgpu.conf.txt (2.6 KB)
I perform a full flash every time (sudo ./flash.sh auto2-gpgpu mmcblk0p1)

What steps do I need to do in order to check if my configuration is correct and to be able to recognize the external NVME drive with the Orin SoMs?

Hi,

Please just follow up previous thread and continue the check ODMDATA.

@WayneWWW , do you want them to go back and update the earlier post? It appears to be locked now.

@smcentee, when you do the signal probe and convert the hex values of the bit fields, what values are you getting from the T234 table?

The hex value for the flash attempt that boots is:
0x40800000

My conf file with ODMDATA defined looks like:

source “${LDK_DIR}/p3701.conf.common”;

PINMUX_CONFIG=“Orin-jetson_agx_orin-pinmux.dtsi”;

BPFDTB_FILE=“tegra234-bpmp-3701-0000-3737-0000.dtb”;
DTB_FILE=“tegra234-umc-gpgpu.dtb”;
TBCDTB_FILE=“tegra234-umc-gpgpu.dtb”;
#DTB_FILE=“tegra234-p3701-0000-p3737-0000.dtb”;
#TBCDTB_FILE=“tegra234-p3701-0000-p3737-0000.dtb”;
EMMC_CFG=“flash_t234_qspi_sdmmc.xml”;
OVERLAY_DTB_FILE=“${OVERLAY_DTB_FILE},tegra234-p3737-camera-dual-imx274-overlay.dtbo,tegra234-p
3737-camera-e3331-overlay.dtbo,tegra234-p3737-camera-e3333-overlay.dtbo,tegra234-p3737-camera-i
mx185-overlay.dtbo,tegra234-p3737-camera-imx390-overlay.dtbo,tegra234-p3737-audio-codec-rt5658-
40pin.dtbo,tegra234-p3737-overlay.dtbo”;
ODMDATA=“gbe-uphy-config-0,nvhs-uphy-config-1,hsio-uphy-config-16,hsstp-lane-map-3”;

Hi,

As I already told in previous post… the document already told you how to check whether ODMDATA is correct in each bit. Please check it by yourself first.

If ODMDATA is correct and all the patches mentioned by document is already added, then needs to check from hardware signal aspect.

I’ve checked it and let me go through my thinking. My value is 0x40800000.

So, from the chart-
bits 31-26 → 010000 = 16 → HSIO UPHY Config (Correct)
bits 25-23 → 001 = 1 → HSIO UPHY Config (chart says HSIO UPHY Config, but guessing its Config Number in NVHS UPHY Lane Mapping Options) (so 1 is correct for NVHS - Endpoint Mode)
bits 22-18 → 00000 = 0 → GBE UPHY Config (GBE is not configured, so correct).

So if I understand this correctly, my ODMDATA is being set correctly to my settings in the .conf file. Is that correct?

The patches I added were mentioned above to the appropriate files.

If so, why then when you had me convert the tegra234-bpmp-3701-0005-3737-0000.dts file using the dtc tool, those values were incorrect?

The value will get changed during flash with the combination between config file and original bpmp dtb. Since you only convert the original dtb, the value could be mismatched.

It is okay to ignore that if runtime ODMDATA is expected value.

I’m making some progress but still not fully there yet. According to a few forum posts, I found a parameter in the dtsi file at /hardware/nvidia/soc/t23x/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi.

I modified the 14180000 & 141e0000 controller nodes to be ‘status=okay’.

Now after full flashing, the dmesg log of the Orin is showing (more than I had before):

[ 6.539233] tegra194-pcie 14180000.pcie: Adding to iommu group 9
[ 6.551633] tegra194-pcie 14180000.pcie: Using GICv2m MSI allocator
[ 7.775072] tegra194-pcie 14180000.pcie: Using GICv2m MSI allocator
[ 7.796938] tegra194-pcie 14180000.pcie: host bridge /pcie@14180000 ranges:
[ 7.804122] tegra194-pcie 14180000.pcie: IO 0x0038100000…0x00381fffff
→ 0x0038100000
[ 7.812817] tegra194-pcie 14180000.pcie: MEM 0x2728000000…0x272fffffff
→ 0x0040000000
[ 7.829555] tegra194-pcie 14180000.pcie: MEM 0x2440000000…0x2727ffffff
→ 0x2440000000
[ 8.945332] tegra194-pcie 14180000.pcie: Phy link never came up
[ 8.951505] tegra194-pcie 14180000.pcie: PCI host bridge to bus 0000:00

Attached is the grep of dmesg “pcie”
dmesg-grep-pcie.txt (9.5 KB)
It looks like none of the DT connector links are coming up, so I must be missing something.

How do I get the Phy link up for C0? I followed Step 1 I mentioned above, but unsure of how to complete Steps 2 & 3.

Can you please provide examples, if this is my problem?

Hi,

If you just scroll down more in the document which you are reading now… then you will see the examples…

https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#enable-pcie-in-a-customer-cvb-design

As what I keep telling in this post and previous post, what you are doing now is already done by many other users/partners before. The document has the sample already. Make sure you did that device tree change first…

Also, please also try other kind of NVMe during the test too. Sometimes it is pcie device side has special requirement to get link detection. What you are doing now is just general setup, it won’t do that kind of work.

For example, if you test 3 kinds of NVMe SSD, and 2 of them can work, then it means those general setup is correct and done. No need to repeat the checking why it cannot detect the rest one of the SSD.

I modified those 3 files (tegra234-p3737-pcie.dtsi, tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi, & tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi) exactly according to the above document you showed. Is that all that is needed? It doesn’t show steps 2 and 3, so wanted to check.

I know others have had same issue in the forums, but did not see solutions (i.e. how to add the ‘pipe2uphy’ command or ‘reset-gpios’ command, for example).

When you said ‘Make sure you did that device tree change first’, what do you mean? Activate the C0 & C7 via the tegra234-soc-pcie.dtsi file, i.e. change the status to “okay” and not “disabled”?

We are using the same nvme m.2 SSDs that we used in our Xavier solution, without any issue there.

You already added pipe2uphy when you put those phys things into your kernel device tree.

And (3) is talking about if the “Tegra PCIe is operated in endpont mode”. This is not for your case… your Tegra PCIe is operated in root port mode so that it can work with your PCIe endpoint device (NVMe SSD)…

Please don’t think the situation too complicated… The only 2 things you need to do

  1. The odmdata configuration.
  2. The all change that happens in the example change block… (you can ignore C7 part)

This will make the general setup done. Nothing else is needed.

OK, so the tegra234-soc-pcie.dtsi doesn’t need to be updated? I wasn’t getting anything for tegra194-pcie 14180000 via dmesg before I made that change. I’ll try changing it back to “DISABLED”

So you are saying just performing those two steps above, the nvme ssd should be recognized on my pcie?

They should be compatible in both correct?

OK, so the tegra234-soc-pcie.dtsi doesn’t need to be updated? I wasn’t getting anything for tegra194-pcie 14180000 via dmesg before I made that change. I’ll try changing it back to “DISABLED”

It is just device tree syntax rules… I can have 100 locations to enable 14180000 different from tegra234-soc-pcie.dtsi … there is no rule to “must enable or disable it inside tegra234-soc-pcie.dtsi”.
14180000 is also enabled in the screenshot above. …

If you must use tegra234-soc-pcie.dtsi to make 14180000 enabled, then it probably gives a hint that the change you added to tegra234-p3737-pcie.dtsi totally not take effect…

So you are saying just performing those two steps above, the nvme ssd should be recognized on my pcie?

Ideally, if all the patches really take effect.

They should be compatible in both correct?

Not sure. No guarantee. Please always take things as different cases.

I reverted the tegra234-soc-pcie.dtsi file back to the original state.

I recompiled, copied, and full flashed. NVMe not recognized and still getting:

[ 8.945332] tegra194-pcie 14180000.pcie: Phy link never came up
[ 8.951505] tegra194-pcie 14180000.pcie: PCI host bridge to bus 0000:00

Is there anything else I can try to check this interface?

tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi, & tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi

Could you share these two files from your side?

btw, I just notice the screenshot I shared somehow has no detail info for each field.

https://docs.nvidia.com/jetson/archives/r35.5.0/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=pcie#enable-pcie-in-a-customer-cvb-design

Please refer to rel-35.5. doc and it will have full info.

Here are the files (with txt added inorder to upload):
tegra234-mb1-bct-gpio-p3701-0000-a04 1.dtsi.txt (4.7 KB)

tegra234-mb1-bct-pinmux-p3701-0000-a04 1.dtsi.txt (63.6 KB)

Also, yes, I saw those missing fields and found them in another doc.

Here is also my modified tegra234-p3737-pcie.dtsi file
tegra234-p3737-pcie.dtsi.txt (2.1 KB)

please remove TEGRA234_MAIN_GPIO(K, 0) and TEGRA234_MAIN_GPIO(K, 1) from your tegra234-mb1-bct-gpio-p3701-0000-a04 1.dtsi and do full flash.

One more question here. Are you using rel-35.4.1 here or you are using rel-35.5?