AGX Orin UPHY Lane Configuration

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
#1

Hi NV Support Team
From document “Jetson_AGX_Orin_Design_Guide_DG-10653-001_v1.0”
Table 6-4. USB 3.2, PCIe, UFS, and MGBE Mapping Options

Picture 1
Picture 1780×848 159 KB

  1. PCIe x2 (C4), RP (as picture1 shown) is typo from Configuration #1? Actually, it should be PCIe x4 (C4) in configuration #1, right?

  2. PCIe x4 (C5), RP/EP (as picture1 shown) is typo from Configuration #3? Actually, it should be PCIe x8 (C5) in configuration #3, right?

    Picture 2
    Picture 2818×845 158 KB

  3. As Picture 2 shown, we use UPHY0 Block ( Lane 0 to Lane 7 ) as configuration #2, while UHPY1 Block(Lane 0 to Lane ) and UPHY2 Block(Lane0 to Lane7) as configuration #1, could this be OK?

  4. Is Configuration #3 supported or could we use configuration #3 in our own design?

#4
  1. Yes, it is typo.
  2. Yes, it is typo.
  3. No. No mixing usage is supported, you can only choose #1 or #2.
  4. Currently #3 is not supported, please don’t use it.
#5

Got it！Thanks。
Will Configuration #3 be supported in the future?

#6

There is no ETA yet.

#8

Hi NV Support Team,
Configuration 1 only supports one MGBE(MGBE0) , and all lanes of UPHY2 Block can not be used in configuration 1 except LANE 4(UPHY_RX6/TX6),is that right?

#9

Yes.

#10

That’s quite inflexible.
Thank for your support.