AGX OrinUSB 3.2, PCIe, UFS, and MGBE Mapping Options

Hi,
We are planning to use Configuration #1, For PCIe Port C4, is it x2 lane or x4 lane? In this which is Lane 0, 1, 2, 3? Looks like UHPY RX/TX22 should be Lane 0 and UPHY RX/TX11 is lane 3 but its connected otherwise in Development kit? Where can I get this info to be confident.
Since the development kit uses Configuration #1, is only x2 lane supported for M.2 E key? and other connections are for future upgrade?
Same question for PCIe port C5, which is Lane 0 and Lane 7?

Based on the Jetson AGX Orin UPHY Mapping Options query, you have mentioned it as Typo for C5 x4 lane for configuration #3. Is it typo as well for C4 x2 for configuration #1?

Hi, it is x4 for C4. The Lane number is listed in turn (UPHY22 is Lane0 and so on). C1 (x1) is for M.2 E on devkit. Same number in turn for C5 (UPHY1 Lane0 to 7).

Thank you. Do you have ETA for the updated design guide?
In the P3737_A04_OrCAD_schematics.pdf, for C4 and C5 the lane mapping does not match what is provided in Design guide. Could you please let me know which is correct?

Both are correct. C4 is used in reversal mode on P3737 board.

Thank you. Do you know why there is a dependency between the various lanes, i.e. why does the configuration of the bottom section affect the configuration of the top section so that you can’t mix and match?

I don’t understand your question. PCIe port support the reversal lane mapping usage, it might be for better layout.

This question is regarding the mapping options for different configuration. any idea why does the UPHY lane 0 to lane 7 affect the other UPHY lane configuration.

The reason is just we didn’t validate that. So we cannot promise it would work fine.

Thank you for the reply

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