M.2 carrier board schematic

I am working on designing a carrier board for the Orin module. I’ve been following the schematic of the carrier board provided by Nvidia but I have a question regarding the PCIe lane selection for the x4 M.2 M-key slot. In the design guide PDF (Table 7-4, UPHY0 Mapping Options) is says that the PCIe x4 C4 controller uses these lanes:
UPHY_RX22/TX22 → Lane 4
UPHY_RX23/TX23 → Lane 5
UPHY_RX10/TX10 → Lane 6
UPHY_RX11/TX11 → Lane 7
And in the example design the following connections are made:
UPHY_22 → PE3 (Lane 4)
UPHY_23 → PE2 (Lane 5)
UPHY_10 → PE1 (Lane 6)
UPHY_11 → PE0 (Lane 7)

I don’t have tons of experience with PCIe but I would have expected:
lane 4 → PE0
lane 5 → PE1
lane 6 → PE2
lane 7 → PE3

Does it matter? Should I reverse the order? I am planning to make a second x4 M.2 adaptor slot using UPHY1 x8, controller C5. I would have connected lanes 0-3 to PE0-PE3 on the connector until I noticed this weirdness on the example design.

I should also point out that the x8 connector uses the ordering I would expect for C5, although it continues beyond the first 4 lanes. IE PE0 is lane 0/UPHY12, PE1 is lane 1/UPHY13, etc.

One controller can be used for one port only. In your case, x8 port can only be used for one port only. Reverse mapping is supported. Please refer to the Orin Design Guide doc in DLC for more info.

Hi, thanks for the response.

For anyone else interested in this topic here’s a link to a decent discussion of lane reversal is:
https://www.teledynelecroy.com/doc/understanding-lane-reversal-and-polarity

Lane reversal is possible by the PCIe standard (lane 0 → PE3, lane 1 → PE2 etc) and is an option to make PCB routing easier and avoid dealing with crossing traces.

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.