I am working on designing a carrier board for the Orin module. I’ve been following the schematic of the carrier board provided by Nvidia but I have a question regarding the PCIe lane selection for the x4 M.2 M-key slot. In the design guide PDF (Table 7-4, UPHY0 Mapping Options) is says that the PCIe x4 C4 controller uses these lanes:
UPHY_RX22/TX22 → Lane 4
UPHY_RX23/TX23 → Lane 5
UPHY_RX10/TX10 → Lane 6
UPHY_RX11/TX11 → Lane 7
And in the example design the following connections are made:
UPHY_22 → PE3 (Lane 4)
UPHY_23 → PE2 (Lane 5)
UPHY_10 → PE1 (Lane 6)
UPHY_11 → PE0 (Lane 7)
I don’t have tons of experience with PCIe but I would have expected:
lane 4 → PE0
lane 5 → PE1
lane 6 → PE2
lane 7 → PE3
Does it matter? Should I reverse the order? I am planning to make a second x4 M.2 adaptor slot using UPHY1 x8, controller C5. I would have connected lanes 0-3 to PE0-PE3 on the connector until I noticed this weirdness on the example design.