UPHY Options on Orin

Are all the options (PCIe, USB, UFS and MGBE) available for UPHY6, 7, 8 and 9? Specifically, can I program UPHY6 to USB3.1 when using the AGX Orin ?

Please check out our design guide: Jetson Download Center | NVIDIA Developer
In Chapter 6 we highlight how the UPHY lanes can be used for PCIe, USB, UFS and MGBE. Some of the lanes have overlapping functionality. For example UPHY0 Lane 0 can be used either for PCIe x1 or USB 3.2.

Thank you leelak for the information. It is still a little unclear to me if you can only have Function #1 or Function #2 or can you selection UPHY lane function separately.

We have a carrier board that complies with these AGX Xavier lane settings.

From table 5 of the migration guide:

If I plug an Orin in place of the Xavier, can I set the lanes of the Orin to support the USB and PCIe attached to UPHY6-9?


Orin only has PCIe (Ctrl 7) or MGBE on the UPHY [9:6]. You can only use the functions from either Function #1 and Function #2. You can leverage the below configuration for all three USB ports and PCIe x1 & PCIe x4.

Thanks leelak. That settles the question for us.

Best Regards,

Still unclear pin mapping understanding…

Why is the PDF only showing Function #1, Function #2 while the Jetson_AGX_Orin_Pinmux_Config_Template.xlsm is showing SFIO0 - SFIO4 Pinmuxing Options?
What is correct and/or why the different naming conventions?
Does UPHY2 also support PCIe x4 (C7) beside 4x MGBE as shown in SFIO0 Column at the UPHY2 Rows?

Also UPHY0 seams to have more Special Function Mapping according to the Excel Table compared the the PDF Datasheet (DG-10653-001_v0.2) or Migration Guide (DA-10655-001_v0.2)

Is there something missing about C0 to C7 mappings that is not taking into account in the Excel Table and would explain it?

Only the mapping shown in the design guide document are supported. Please do not use the pinmux to guess what might support or not support.

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