UPHY lane v.s. SerDes lane

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
, , ,
1

Hi Sir,
As title, what is the difference between UPHY lane & Serdes lane ?
Is a UPHY lane originated from a PCIe bus ?
What’s the logic behind it to distribute the UPHY lanes to high speed interface like PCIe, USB, UFS, M.2…and so on ?
How to config ODMDATA for that?

I know that my question might be basic. but could you provide more information ?

Thanks.

Jimmy

4

UPHY supports multiple interfaces like PCIe, USB3, MGBE. UPHY lane assignment/configuration needs to be one of the supported configurations in the design guide. ODMDATA allows to choose between supported UPHY lane configurations. Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide

6

@sgursal
Thanks for the reply.
Three more questions:

  1. According to the block diagram of CVB p3737, specific UPHY lane are assigned to USB ports, as circled by red line as below:

    image
    image645×564 149 KB

    My question is : how to assign a UPHY lane to a specific USB port ? Or there is a mapping table, for the 4 USB 3.2 ports & 4 USB 2.0 ports ?

  2. How to map UPHY Lane 0 ~ UPHY Lane 23 to UPHY00~UPHY07, UPHY10~UPHY17 & UPHY20~UPHY27 ?

  3. PCIe x 16 slot is used with 8 UPHY lanes, as below:
    image

Why ? How about the missing upper x8, for x16 ?

Thanks.

Jimmy

7

For UPHY lane mapping please refer to Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide

and for USB porting please refer to Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide

8

@sgursal
Thanks for the prompt reply.

1. Please check the diagram & table below:

image
image1017×401 113 KB

image
image990×458 39.1 KB

By the document you refer to, where is USB3 assigned with UPHY20 ?

  1. Following 1), P1 or P2 might be the USB port (3.2) for flashing. But inside the dtb, as below:
    image
    image679×527 13.9 KB

flashing port seems to be usb 2.0.

It is confusing.

  1. And I see no information about how to map UPHY Lane 0 ~ UPHY Lane 23 to UPHY00~UPHY07, UPHY10~UPHY17 & UPHY20~UPHY27 @ that document.

Please advise. Thanks.

Jimmy

10

Hi,

For the usb question I would suggest you could read the document first.

What I saw here is you just didn’t know how the device tree for USB part works

Flash port is a port supports both USB3 +USB2… so it would have usb2 lane + usb3 lane in use together.

Also, you actually should check table as below in the design guide. UPHY20 is USB3.2 P2.

image
image1300×592 56.4 KB

11

@WayneWWW
Thanks for the prompt reply.

I will spend some time reading Adaptation_and_Bringup_for_Jetson_AGX_Orin

BTW, could you provide the link to the table "7.4 UPHY0 mapping options (USB & PCIE) ?
Since I can’t find it at
Welcome — NVIDIA Jetson Linux Developer Guide

Thanks.

Jimmy

12

Did you ever read the design guide before?

13

@WayneWWW
Hi Wayne,
I only read Linux developer guide, and I missed the design guide somehow.
Anyway, many thanks~

Jimmy

1 Like
14

@WayneWWW
One more question:
Please check the attached default dtb, as below:

image
image494×335 7.78 KB

and

image
image678×368 24.1 KB

So, the OTG port is usb2-0\usb3-0.

But , according to the attached below:

image
image391×689 16.6 KB

USB3-1 claims that its USB2 companion port is USB2-0.

Is there any conflict here ?

Thanks.

Jimmy

15

The phy-names in usb@3550000 are just a fixed string. It does not really link to any USB lane.
In brief, no matter what usb3 node you added there, this phy-names is always usb2-0/usb3-0.

Only the nvidia,usb2-companinon field represents the true link.

16

@WayneWWW
Many thanks!

Jimmy