HI all,
I followed the official process to enable pcie endpoint mode, my hardware is currently two 36.3 orin and x4 pcie cables, will the C5 be compatible with x4 cables? I don’t know if I can read the pci information from the RP again, after following the process to turn on echo 1 > controllers/141a0000.pcie_ep/start, the RP can’t recognise it and I can’t get any information about the BAR area from the EP again!
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will the C5 be compatible with x4 cables
可以
I don’t know if I can read the pci information from the RP again, after following the process to turn on echo 1 >controllers/141a0000.pcie_ep/start, the RP can’t recognise it and I can’t get any information about the BAR area from the EP again!
請重開你的RP.
Thanks for your response！
and i want to know, if i just set orin ep mode , just followed the official process, dont open RP orin ,can i get the information from dmesg | grep pci_epf_nv_test , when i set echo 1 > controllers/141a0000.pcie_ep/start , i get nothing.
Thanks
I remember there should be some log. Maybe you could share the dmesg first.
Hi,these are my logs about two mode ,Looking forward to your reply！lspci is nothing to display
ep_orin_log.txt (68.5 KB)
rp_orin_log.txt (70.7 KB)
你的EP端根本就沒有做PCIe EP的設定… 整個driver都還在當跑RP …
我直接参考的这个步骤进行设置，有需要其他进行设置的东西么，例如设备树的修改等等。
A Jetson device must be flashed in a specific way to enable PCIe endpoint mode:
p3701.conf.common file.#. Set the nvhs-uphy-config of the ODMDATA value, for example: ODMDATA="**gbe-uphy-config-22,nvhs-uphy-config-0,hsio-uphy-config-0**,gbe0-enable-10g,hsstp-lane-map-3"; to ODMDATA="**gbe-uphy-config-22,nvhs-uphy-config-1,hsio-uphy-config-0**,gbe0-enable-10g,hsstp-lane-map-3";
This step completely erases data that was previously stored on the Jetson device.
2. Edit the p3701.conf.common file again and restore the ODMDATA property’s original value.This step ensures that devices that were flashed in the future will operate in PCIe root port mode.
喔 抱歉 搞錯平台. 以為你在用Orin NX. 如果是Orin AGX的話設定有開.
請確認一下/proc/interrupts最底下的pcie EP的interrupt有沒有跟著你的start之後進行增加
類似
# cat /proc/interrupts | grep pci
201: 1 0 0 0 0 0 0 0 GICv3 77 Level tegra-pcie-intr, PCIe PME, aerdrv
203: 0 0 0 0 0 0 0 0 GICv3 83 Level tegra-pcie-intr
205: 3 0 0 0 0 0 0 0 GICv3 85 Level tegra-pcie-ep-intr
239: 4 0 0 0 0 0 0 0 2200000.gpio 153 Edge tegra_pcie_5_pex_rst_irq
这是log信息
proc_interrupt_log.txt (20.3 KB)
看错勒，是有的
202: 0 0 0 0 0 0 0 0 GICv3 77 Level tegra-pcie-intr
204: 0 0 0 0 0 0 0 0 GICv3 83 Level tegra-pcie-intr
206: 0 0 0 0 0 0 0 0 GICv3 85 Level tegra-pcie-ep-intr
288: 7 0 0 0 0 0 0 0 2200000.gpio 153 Edge tegra_pcie_5_pex_rst_irq
請問這是在兩台Orin devkit上做測試嗎?
对的是两台 agx orin ，设备配套是相同的，我看之前的log 里面有说 pcie 电压问题 例如
[ 33.760429] VDD_3V3_PCIE: disabling
[ 33.760446] VDD_12V_PCIE: disabling
会不会和这个相关，还有排线对这个会不会有很大的影响
对了，我还有一个问题，func1 的注册是ep端每次开机都需要去做的操作么，
谢谢
哦，我们现在用的是自己的设备树文件，底板是我们自己的套件
这是我在设备树下找到的相关信息tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi
pcie-ep@141a0000 {
nvidia,refclk-select-gpios = <&gpio
TEGRA234_MAIN_GPIO(Q, 4)
GPIO_ACTIVE_HIGH>;
};
tegra234-soc-overlay.dtsi
pcie-ep@141a0000 {
pinctrl-names = “default”;
pinctrl-0 = <&pex_rst_c5_in_state>;
nvidia,host1x = <&host1x>;
num-ib-windows = <2>;
num-ob-windows = <8>;
};
tegra234-p3737-0000+p3701-0000.dts
pcie-ep@141a0000 {
status = “disabled”;
vddio-pex-ctl-supply = <&vdd_1v8_ls>;
reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
nvidia,refclk-select-gpios = <&gpio_aon
TEGRA234_AON_GPIO(AA, 4)
GPIO_ACTIVE_HIGH>;
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
"p2u-5", "p2u-6", "p2u-7";
};
排線設計請參考
你好，我现在准备进行替换，将ep 端换成Orin devkit ，rp端还是现在套件，现在的套件是经过验证能够正常使用的，这样可以么