Enabling Orin Dev Kit PCIe EP mode

Hi,

Wanting to set Orin Dev Kit as an endpoint PCIe C5 EP to be connected over PCIe crossover cable, and am following instructions under Enable PCIe in a Customer CVB Design.

Step 1: in p3701.conf.common edit line 164 to configuration #2, ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,hsio-uphy-config-16,**nvhs-uphy-config-0”;. There is broken link to T23x BCT Deployment Guide.

Step 3: in Jetson_AGX_Orin_Pinmux_Config_Template_082422.xlsm, edit rows 205:283 columns AS, AT, AY to GPIO(rsvd1), SFIO(PE*_CLKREQ_L), Input where * is 0-10. Changing column “Customer Usage” to respective values is not allowed, “This value doesn’t match the data validation restrictions defined for this cell.”?

Step 2 (listed after step 3.): in tegra234-p3737-pcie.dtsi line 43 under pcie_ep@141a0000 node “Add the pipe2uphy phandle entries as a phy property” “pipe2uphy DT nodes are defined in SoC DT”. Can’t find those values from tegra234-soc-pcie.dtsi below line 417 under node pcie_c5_ep: pcie_ep@141a0000. It is not clear what is the syntax for pipe2uphy, is it referring to phys, phy-names, also is status = “disabled”; supposed to be enabled?

Step 3 (listed after first step 3.): in tegra234-p3737-pcie.dtsi line 43 under pcie_ep@141a0000 node, “add the reset-gpios property with the gpio phandle, the gpio number connected to PERST# and flags(GPIO_ACTIVE_LOW)”. It is not clear what is the syntax for reset-gpios, gpio handle number?

Can these steps be given little more clarity as to what is the exact correct syntax of expected entries, or an example like patch given for PCIe x1 (C0), PCIe x8 (C7) in RP, just for PCie C5 EP pcie_ep@141a0000?

Thanks.

Hi,

Is this is devkit case, I don’t think you need to do those work on pinmux/device tree. It shall be handled already.

https://docs.nvidia.com/jetson/archives/r35.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=endpoint

Hi,

So steps in Enable PCIe in a Customer CVB Design should be skipped and steps in Bring up Tegra PCIe Endpoint Mode will still put C5 into EP mode (pcie_ep@141a0000), even though section uses Tegra, Xavier, Orin interchangeably?

In subsection Hardware Requirements for a Tegra PCIe Endpoint Mode:

Step 3: is Orin crossover cable same as Xavier Jetson_AGX_Xavier_PCIe_Endpoint_Design_Guidelines.pdf Figure 3.?

In subsection Enabling the PCIe Endpoint on a Jetson AGX Orin Devkit:

Step 1: p3701.conf.common leave config #1 edit ODMDATA=“gbe-uphy-config-22,hsstp-lane-map-3,nvhs-uphy-config-1,hsio-uphy-config-0,gbe0-enable-10g”;
Step 2: flash Orin with sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1

In subsection Connecting and Configuring the Tegra PCIe Endpoint System:

Step 3: once booted, not sure if mount -t configfs none /sys/kernel/config needs to be executed (pci-endpoint-cfs.rst line 20)? Edit /sys/kernel/config/pci_ep/functions/pci_epf_nv_test/func1/vendorid and deviceid. If /sys/kernel/config/pci_ep/controllers/141a0000.pcie_ep/start shows up, edit. Boot RP system, proceed to Testing PCIe Endpoint Support steps.

Thanks.