Hi,
So steps in Enable PCIe in a Customer CVB Design should be skipped and steps in Bring up Tegra PCIe Endpoint Mode will still put C5 into EP mode (pcie_ep@141a0000), even though section uses Tegra, Xavier, Orin interchangeably?
In subsection Hardware Requirements for a Tegra PCIe Endpoint Mode:
Step 3: is Orin crossover cable same as Xavier Jetson_AGX_Xavier_PCIe_Endpoint_Design_Guidelines.pdf Figure 3.?
In subsection Enabling the PCIe Endpoint on a Jetson AGX Orin Devkit:
Step 1: p3701.conf.common leave config #1 edit ODMDATA=“gbe-uphy-config-22,hsstp-lane-map-3,nvhs-uphy-config-1,hsio-uphy-config-0,gbe0-enable-10g”;
Step 2: flash Orin with sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1
In subsection Connecting and Configuring the Tegra PCIe Endpoint System:
Step 3: once booted, not sure if mount -t configfs none /sys/kernel/config needs to be executed (pci-endpoint-cfs.rst line 20)? Edit /sys/kernel/config/pci_ep/functions/pci_epf_nv_test/func1/vendorid and deviceid. If /sys/kernel/config/pci_ep/controllers/141a0000.pcie_ep/start shows up, edit. Boot RP system, proceed to Testing PCIe Endpoint Support steps.
Thanks.