The Jetson AGX Orin Devkit PCIe Configuration

Jetson AGX Orin (Root point) and FPGA VCU 118 (end point), communicating through a pcie device, I want to modify my Jetson’s pcie controller to C5 Root point mode, how do I modify ODMDATA?


Image from: (Jetson AGX Orin Platform Adaptation and Bring-Up — Jetson Linux<br/>Developer Guide 34.1 documentation)
Also do I need to make changes in this, what does CVB design mean here, I couldn’t find a definition on google

你應該要先告訴我們你現在在用NV devkit還是自己的底板…

不過不管你的結論是什麼, 你現在的問題其實沒什麼幫助 因為我們預設C5本來就是RP mode. 根本不用額外做其他設定. ODMDATA也不用改

jetson采用的是
image
FPGA采用的是 AMD Virtex UltraScale+ FPGA VCU118 评估套件 (xilinx.com)

那你什麼都不用改 預設的software就已經是RP mode了…

但是为什么,连接Jetson和FPGApice端口,FPGA的pcie链路灯并不点亮呢?但是主机和FPGA的链路灯可以点亮?

這邊說明一下

  1. 如果你能接其他pcie device, 比方說網卡到你的C5 slot上面, 然後Jetson Orin也能讀到這張網卡, 那你前面想問的"怎麼把這個C5進到RP mode"就不是個問題.
    而且這件事情不太需要驗證的原因是
    ->你用的是Jetson Orin AGX devkit. 這東西的C5我們幾乎天天在用, 預設就是RP mode. 除非你自己把軟體改掉讓C5沒辦法正常工作, 不然我認為沒什麼好額外設定的 (或是你用的根本不是Orin AGX devkit /BSP軟體版本太舊)

  2. FPGA本來狀況就會比其他PCIe device多, 比方說Jetson端可能開機之後可能得等你的FPGA一下子才能做link detection. 這種時候讓pcie driver 晚點手動unbind/bind再跑一次或許有幫助. 另外Jetson PCIe沒有支援hotplug.

另外這個debug tip才是你應該要參考的.
https://docs.nvidia.com/jetson/archives/r35.4.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=orin%20adaptation#debug-pcie-link-up-failure

Nv团队你好,很抱歉第二天才回复你,我看到了debug tip 链接,您提到的C5 pcie控制器是否是和FPGA链接?还是ARM?如果是和FPGA链接,需要修改pcie设备树里面的电压吗?( Jetson AGX Orin board not able to enumerate FPGA PCIe card (Latest kernel 35.1.0) - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums ~ Jetson AGX Orin 板无法枚举 FPGA PCIe 卡(最新内核 35.1.0) - Jetson 和嵌入式系统 / Jetson AGX Xavier - NVIDIA 开发者论坛

您提到的C5 pcie控制器是否是和FPGA链接?还是ARM?

說實話我真的不知道你在問我什麼…

如果你在用rel-35.4.1 BSP那你什麼都不用改. 這邊該設定的都已經設定了

Hi, it may be that my previous description was not quite standard, can you refer to the following for some advice
Current environment Jetson agx orin &&VCU118 (EK-U1-VCU118-G)
hardware
jetson (64gb)


FPGA

pcie*16 expansion cable

software
jetson adopted 35.4.1
pcie mode C5 root (already flashed with SDKmanager, no modifications)

Connection experiment

Jetson is powered on, Jetson and FPGA are not connected, after typing dmesg | grep pcie on the Jetson side the log is as follows:
no link log.txt (2.9 KB)

After Jetson and FPGA are connected via pcie, after burning the code on the fpga side, start Jetson, and enter dmesg | grep pcie on the Jetson side, the log is as follows:
link lod.txt (93.2 KB)

As you can see, the Jetson and FPGA links are not connected, the PCIe link light on the FPGA board is not lit, we tried different pcie connection cable lengths (10cm, 40cm), tried the method of modifying the voltage in the Nvidia forums ([Jetson AGX Orin board not able to enumerate FPGA PCIe card (Latest kernel 35.1.0) - Jetson & Embedded Systems / Jetson AGX Xavier - NVIDIA Developer Forums](https://forums.developer.nvidia.com/t/ jetson-agx-orin-board-not-able-to-enumerate-fpga-pcie-card-latest-kernel-35-1-0/226733)), none of the above worked. It is possible to rule out the PCIe connection cable and the code on the FPGA side, as we have already implemented communication between the FPGA and the host computer. Can you provide me with some direction?

  1. FPGA本來狀況就會比其他PCIe device多, 比方說Jetson端可能開機之後可能得等你的FPGA一下子才能做link detection. 這種時候讓pcie driver 晚點手動unbind/bind再跑一次或許有幫助. 另外Jetson PCIe沒有支援hotplug.

前面這裡有提到步驟, 請問你試過了嗎

You may not understand what I mean, I was doing the experiment about the communication between host and FPGA, after uninstalling the xdma driver on the host side, when the FPGA side code is burned, the pcie link light will be lit automatically, and I don’t need to detect it manually, even if the driver doesn’t exist, the link light can be lit after the code is burned, so I’m now on the jetson side, so I don’t have to install the xdma driver. What you said does not support hot-plugging, I did not do the pcie device connection during the code burning process, my experimental sequence is: 1 pcie connection Jetson and FPGA; 2 FPGA power on and off, FPGA burn code successfully, Jetson device power on and off, and I also tried to reboot the jetson, and it did not work. If the appeal jetson device is replaced by the host, then after the FPGA code is burned, the link light on the FPGA will automatically light up without any other operation, which has nothing to do with whether or not the driver is installed on the host side. I don’t know if you have read the log of link log.txt that I sent out before, which shows the following


And I’ve tried the steps you mentioned and they didn’t work.

如果你是在說AER error的話

最準確的方法就是你們去弄到一個pcie analyzer然後抓LA trace.

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