AGX Orin 32GB 核心板，底板是我们自己设计的。使用 PCIE 与Xilinx FPGA开发板链接， C5控制器，8 lane 用了 4 lane，但结果是 ：
[ 9.578953] tegra194-pcie 141a0000.pcie: Adding to iommu group 50
[ 9.733463] tegra194-pcie 141a0000.pcie: host bridge /bus@0/pcie@141a0000 ranges:
[ 9.733488] tegra194-pcie 141a0000.pcie: MEM 0x2800000000…0x2b27ffffff → 0x2800000000
[ 9.733494] tegra194-pcie 141a0000.pcie: MEM 0x2b28000000…0x2b2fffffff → 0x0040000000
[ 9.733497] tegra194-pcie 141a0000.pcie: IO 0x003a100000…0x003a1fffff → 0x003a100000
[ 9.733853] tegra194-pcie 141a0000.pcie: iATU unroll: enabled
[ 9.733856] tegra194-pcie 141a0000.pcie: Detected iATU regions: 8 outbound, 2 inbound
[ 10.841383] tegra194-pcie 141a0000.pcie: Phy link never came up
[ 11.842870] tegra194-pcie 141a0000.pcie: Phy link never came up
[ 11.842990] tegra194-pcie 141a0000.pcie: PCI host bridge to bus 0005:00
[ 11.849679] pcieport 0005:00:00.0: Adding to iommu group 50
[ 11.849820] pcieport 0005:00:00.0: PME: Signaling with IRQ 204
[ 11.850314] pcieport 0005:00:00.0: AER: enabled with IRQ 204
检测不到FPGA开发板的任何信息，但FPGA开发板被 RESET后，可以正常工作(可以输出图像)
PADCTL_PEX_CTL_2_PEX_L5_CLKREQ_N_0寄存器的值为：0x460，
PADCTL_PEX_CTL_2_PEX_L5_RST_N_0 寄存器的值为：0x420，满足TRM手册里的说明，
但 PCIE_RP_APPL_DEBUG_0 (地址为 0x141a00d0) 的值是 0xFFFFFFFF
刷机后的版本信息：
jetson@tegra-ubuntu:~$ cat /etc/nv_tegra_release
R36 (release), REVISION: 4.3, GCID: 38968081, BOARD: generic, EABI: aarch64, DATE: Wed Jan 8 01:49:37 UTC 2025
针对PCIE的配置(设备树，ODMDATA)都没有更改，直接使用官网BSP包里的默认配置
期望能给出一些指导意见，谢谢大家！！