Tegra194-pcie 141a0000.pcie: Phy link never came up

[757319640]

Hello nvidia team, I enable the pcie C5 node according to the R35.1 guide, set pcie@141a0000 in the regra234-3701-0004-pat737-0000.dtb file to “okay”, and set it in tegra234-mb1-bct-pinmux-p3701 In -0000.dtsi, set tegra234-mb1-bct-pinmux-p3701-0000.dtsi, pex_l5_clkreq_n_paf0 to: pex_l5_clkreq_n_paf0 {
nvidia, pins = “pex_l5_clkreq_n_paf0”;
/nvidia,function = “pe5”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;/
nvidia,function = “rsvd1”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};

pex_l5_rst_n_paf1 {
nvidia,pins = “pex_l5_rst_n_paf1”;
/nvidia,function = “pe5”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;/
nvidia,function = “rsvd1”;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
But the log shows: tegra194-pcie 141a0000.pcie: Phy link never came up

dmesg.txt (3.1 MB)
tegra234-mb1-bct-gpio-p3701-0000.dtsi (3.8 KB)
tegra234-mb1-bct-pinmux-p3701-0000.dtsi (63.0 KB)
tegra234-p3701-0004-p3737-0000.dtb (331.2 KB)

[WayneWWW]

C5 does not require special configuraiton. It is enabled in the default BSP already.

Please review your hardware as the doucment shows.

https://docs.nvidia.com/jetson/archives/r35.3.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#debug-pcie-link-up-failure

[757319640]

When I use the default C5 node configuration, I use an oscilloscope to measure and find that the reset pin is always pulled low, but the reset pin of the C7 node will change from a low state to a high state when the device starts.

[757319640]

The hardware schematic diagram I use refers to Jetson AGX Xavier. I found that the pin definitions of the carrier board used by the orin module and the Xavier module are the same. My custom carrier board Xavier module can be used normally, but the orin platform cannot be used.
The following is the hardware schematic diagram of my custom carrier board about PCIE，On pages five and nine of the attachment
P2822_B03_OrCAD_schematics.pdf (1.4 MB)

[WayneWWW]

Just a reminder. Please check your flash log to make sure the pinmux file is really the one you want to use…