PCIE REF CLK need AC coupling capacitor or not?

[sagar.kumar2]

Hi,

I have few queries on PCIe side-

1. Please let me know I/O standard used for PCIE REF CLK since as per datasheet AC coupling caps requirement depends on the end point? Please confirm it is HCSL or something else(CML, LVPECL etc)?

2. Can we use UPHY1 in 2x4 bifurcation mode?
   

   

3. As per design guide- CLKreq need 47K Pull up since it is open drain but in carrier board design file there is no pull-up on this trace (PCIE5_CLKREQ_N)?

Thanks
Sagar

[Trumany]

1. It is HCSL signal. AC caps are necessary if the whole line has no AC cap.
2. No, only one controller for UPHY1.
3. There is pull-up on module.

[sagar.kumar2]

regarding Q2-
One root port can identify number of links during link training.

As per you it will work in 1x8, 1x4, 1x2 and 1x1 only

Thanks
Sagar

[Trumany]

@sagar.kumar2

it will work in 1x8, 1x4, 1x2 and 1x1 only

Yes, it only supports 1x8/4/2/1.

[sagar.kumar2]

Hi Trumany,

1. If my retimer REFCLK input is HCSL I/O standard, then do we need AC caps on it?

2. If i am going to use MGBE controller (C0) of UPHY2 i.e. Lane 4, then can we use Lane0 to lane3 as a x4 PCIe RP?

Thanks
Sagar

[Trumany]

1. I am not sure about retimer design, you may add AC caps as backup.
2. No, you can see the info in DG: Only one of the supported configurations per UPHY block can be used in a
   design.