I have designed an electronic card that has Nvidia TX2 and a Intel FPGA Stratix V. Their PCIe design is referencing the schematics of Jetson TX2 development kit and Intel FPGA Stratix V development kit which do not have any termination resistors in their respective schematics for PCIe reference clock. In an earlier chat Jetson TX1/TX2 PCIE differential reference clock type , a question was posted about the I/O standard of TX2 PCIe reference clock and it was replied by Nvidia moderator Trumany that it is HCSL. Within Intel FPGA, I configured it to receiver PCIe reference clock as HCSL I/O standard.
When I encountered intermittent behaviour of the PCIe interface : there are times when TX2 cannot detect the Intel FPGA PCIe device with lspci command, there are also times when during TX2 boot up, there are PCIe error messages running non-stop. I did a measurement of the TX2 PCIe clock with an oscilloscope and discovered that the TX2 PCIe clock is not HCSL. A HCSL clock should be toggling between 0mV and 700mV. The measured has an positive offset voltage of about 600mV and toggling of about 150mV swing, riding on top of the 600mV. This signal appears to be more like a LVDS signal although LVDS should have a 1.2V positive offset voltage. As LVDS receiver can tolerate quite a wide variation of input offset voltage. I reconfigured Stratix V FPGA to receive the clock as LVDS receiver. With this change, the intermittent situations improve significantly with many previously failed electronic cards working. However, there are still failed cases.
I also measured the PCIe clock resistance to ground with a multimeter and received a very high resistance value. This means there is no 50 ohm termination to ground within TX2 for this PCIe differntial clock as shown in Phoenixlee’s last post.
According to Intel FPGA support, its PCIe Hard IP should be configured to receive PCIe clock as HCSL receiver and not LVDS receiver. May I know if it is possible to configure TX2 to output a HCSL PCIe clock ? Or can Nvidia advise how to convert its PCIe clock signal to HCSL ? Or can I provide a separate HCSL clock source to Intel FPGA, not using TX2 PCIe clock source ? Please provide details of the TX2 PCIe clock specification to clarify.