TX2 PCIe clock issue

Using Busybox devmem command, I managed to read back and write the registers. I tried the following :

read back of register T_PCIE2_PADS_REFCLK_BIAS (address 0x100030D0) with 0x28, this is the recommended setting from the Tuning Guide
read back of register T_PCIE2_PADS_REFCLK_CFG0_0(address 0x100030C8) with 0x80B880B8
read back of register T_PCIE2_PADS_REFCLK_CFG0_1(address 0x100030CC) with 0x000480B8

I have a oscilloscope to measure 1 of the 3 PCIe reference clock on my Printed Circuit Board, its measured signal is a 600mV positive offset with a 150mV switching clock riding on the positive offset.

when register T_PCIE2_PADS_REFCLK_CFG0_1 (address 0x100030CC) was written with value 0x0004F0B8, the current driver is supposed to increase current drive from 10.4mA to 16mA. This current is supposed to flow through the 50 ohm termination resistors to create voltage increase from 520mV to 800mV. But in observation, the scope only showed an increase in voltage from around 150mV to 200mV. Can Nvidia explain why there is only marginal increase in voltage ?

I saw in TX2 Technical Reference Manual, there is a header file ardev_t_pcie2_pads.h that probably defines all the PCIe PADS registers. May I know how to get it ?

Please also advise how to set the change so that a newly compiled kernel can have changes to these registers. It is because if the PCIe reference clock is not stable to the FPGA, there will be a lot of PCIe error messages during booting and it will deny TX2 from successfully boot up. It will not be possible to use busybox devmem command if TX2 cannot even boot up.

Hui Peng

What is the issue you are facing with the default REFCLK? Any modification to any of those registers is not really recommended.

Hi vidyas,

The following is my post to Nvidia forum about my problem with the TX2 PCIe reference clock


I have designed an electronic card that has Nvidia TX2 and a Intel FPGA Stratix V. Their PCIe design is referencing the schematics of Jetson TX2 development kit and Intel FPGA Stratix V development kit which do not have any termination resistors in their respective schematics for PCIe reference clock. In an earlier chat Jetson TX1/TX2 PCIE differential reference clock type , a question was posted about the I/O standard of TX2 PCIe reference clock and it was replied by Nvidia moderator Trumany that it is HCSL. Within Intel FPGA, I configured it to receiver PCIe reference clock as HCSL I/O standard.

When I encountered intermittent behaviour of the PCIe interface : there are times when TX2 cannot detect the Intel FPGA PCIe device with lspci command, there are also times when during TX2 boot up, there are PCIe error messages running non-stop. I did a measurement of the TX2 PCIe clock with an oscilloscope and discovered that the TX2 PCIe clock is not HCSL. A HCSL clock should be toggling between 0mV and 700mV. The measured signal has an positive offset voltage of about 600mV and toggling of about 150mV swing, riding on top of the 600mV. This signal appears to be more like a LVDS signal although LVDS should have a 1.2V positive offset voltage. As LVDS receiver can tolerate quite a wide variation of input offset voltage. I reconfigured Stratix V FPGA to receive the clock as LVDS receiver. With this change, the intermittent situations improve significantly with many previously failed electronic cards working. However, there are still failed cases.

I also measured the PCIe clock resistance to ground with a multimeter and received a very high resistance value. This means there is no 50 ohm termination to ground within TX2 for this PCIe differntial clock as shown in Phoenixlee’s last post.

According to Intel FPGA support, its PCIe Hard IP should be configured to receive PCIe clock as HCSL receiver and not LVDS receiver. May I know if it is possible to configure TX2 to output a HCSL PCIe clock ? Or can Nvidia advise how to convert its PCIe clock signal to HCSL ? Or can I provide a separate HCSL clock source to Intel FPGA, not using TX2 PCIe clock source ? Please provide details of the TX2 PCIe clock specification to clarify.

Hui Peng

TX2’s REFCLK is internally sourced from CML (neither HCSL nor LVDS) but ideally, it shouldn’t matter because it adheres to the PCIe spec defined values. So, please note that TX2’s REFCLK is PCIe spec-compliant REFCLK.