PCIe Refclk Frequency range

[parth.bhavsar]

Hello Team,

We found that during the PCIe Clock validation on our carrier board by connecting Jetson Xavier NX SOM and Jetson ORIN NX SOM, it is coming around 99.77Mhz while acceptance criteria as per the PCIe standard is as attached.

Also, we have checked this on P3509 Carrier board using Jetson Xavier SOM. Request to check and share your feedback for the same.

1. PCIe Refclk - For Our Carrier board

PCIe1_REFCLK.pdf (141.5 KB)

2. PCIe Refclk - For P3509 Carrier board

PCIE1_REFCLK_Xavier Devkit.pdf (95.2 KB)

[Trumany]

Hi, I don’t get what the issue is. Please share more detail info of your question (the image can’t be seen). As per PCIe , tuning is not supported as you can see in Tuning guide doc, as custom design is expected to follow the Design Guide well.

[parth.bhavsar]

Hello Trumany,

Thanks for the feedback.

Please find attached image for PCIe Refclk specification from PCIe compliance standards of 8GT/s.

PCIe Refclk frequency is not in the min/max range as per the PCIe compliance standard into the Jetson Xavier Devkit (P3509). Same result we observed in our board also. FYI design guideline is followed by us for our custom design board.

So, request to please check and confirm the PCIe Refclk frequency in Devkit.

Request to please share tuning guide document.

Regards,

Parth Bhavsar

PCIe1_REFCLK.pdf (142 KB)

PCIE1_REFCLK_Xavier Devkit.pdf (95.2 KB)

[parth.bhavsar]

Hello Team,

Request to please update on this topic as soon as possible.

Regards,
Parth Bhavsar

[WayneWWW]

Which pcie are you using here?

Are you trying to say that the SSC is not enabled?

[WayneWWW]

The measured refclk with SSC on the signal can result in the lower frequency reading when measured on the scope.

But if you post-process the same waveform with compliance approved tools then you should be able to separate the SSC component and get the actual frequency of the signal.

Can you please check the signal using the following tool?

https://www.skyworksinc.com/en/application-pages/pcie-clock-jitter-tool

[parth.bhavsar]

Hello,

Thanks for the response.
We are using PCIe0 & 1 from Jetson Xavier and PCIe0,1 & 2 from Jetson Orin.

For the SSC we are directly measure the PCIe clock at receiver end on Xavier Kit.

We will check and try to use suggested tool to measure PCIe clock signal and let you know.

Regards,
Parth Bhavsar

[parth.bhavsar]

Hello Team,

Can you please add below mail id, to get response notification?

mahesh.gohil@einfochips.com

Regards,
Parth Bhavsar

[parth.bhavsar]

Hello,

We have tried to measure PCIe0 & 1 Refclk using suggest skywork " Timing - PCIe Clock Jitter Tool". But we got error in tool while uploading .bin file. Could you please check attached .bin file in your machine and share the result for the same?
Also we have attached Tool setup info for your reference.

PCIe1_Refclk_Freq.bin (125.2 KB)
PCIe0_Refclk_Freq.bin (125.2 KB)

Regards,
Parth Bhavsar

[parth.bhavsar]

Hello Team,

Request to please update on this topic as soon as possible.

Regards,
Parth Bhavsar

[parth.bhavsar]

Hello Team,

Can you please update on this topic?

Regards,
Parth Bhavsar

[Trumany]

Hi, please sync with skywork for that first since it is from your oscillosocpe.

On the other hand, you can try disabling SSC. As per the spec of REFCLK with SSC, it will bring in -300~+2800 ppm deviation and so the freq spec will be 99.72 ~ 100.03Mhz. With SSC enabled, average REFCLK frequency (center frequency) would be scaled based on the SSC deviation. Same mentioned in spec as well (refer below snaps). Considering that, measured average REFCLK frequency by you seems to be within spec limit (below table).

	Parameter	Min	Max	Unit
TPERIOD_AVG	Average Clock Period Accuracy	-300	2800	ppm
FREQUENCY_AVG	Average Clock Frequency	99.72	100.03	MHz

[WayneWWW]

To disable SSC on PCIe C0~C4, below software change is needed for bpmp dtb.

--- a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
+++ b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
@@ -1,4 +1,4 @@
 / {
        uphy {
                status = "okay";
@@ -6,4 +6,11 @@
                ufs-config = "UFS_x1_L1";
                nvhs-owner = "PCIE";
        };
+       clocks {
+                       clock@plle {
+                               clk-id = <0x64>;
+                               /* disable ssc on PLLE */
+                               pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
+                       };
+       };
 };