Jetson AGX Xavier as PCIe Root Port - REFCLK question

I could not find any details about REFCLK pins when Jetson AGX Xavier is used as PCIe Root Port.
If I want to use all available PCIe ports, it is obvious that REFCLK pins are outputs, however, available literature does not specify the following:

Are all REFCLK pins buffered version of the same 100MHz reference clock on SoC?
If this is true, then only one REFCLK pin pair (e.g. pins E14 and E15) can be routed to the user’s PCB and then buffered.

If each REFCLK output is independent, then how to control Spread Spectrum Clocking (SSC) or Constant Frequency Clocking (CFC) on each output?

Regards,

Slavisa

NOTE: List of pins used as REFCLK output
E14, E15, F16, F17, F20, F21, F24, F25

Hi, are you talking about PEX_CLK or PEX_REFCLK? They have different usage on root port or endpoint mode. You can check the TRM in DLC to get more information. https://developer.nvidia.com/embedded/downloads#

Hello Trumany,

Thank you for the fast response. Here is the list of pins I am referring to (all are PEX_CLK and we are talking about root port only):

Pin Name
E14 PEX_CLK0_N
E15 PEX_CLK0_P
F16 PEX_CLK1_P
F17 PEX_CLK1_N
F20 PEX_CLK3_P
F21 PEX_CLK3_N
F24 PEX_CLK5_P
F25 PEX_CLK5_N

After searching Xavier TRM (8288 pages), I could not find the following:

  1. “spread” or “spectrum” in chapter 9.4 PCI Express (PCIe) Controller.
  2. If PCI_CLKs are buffered clocks from the same 100MHz clock source (PLL?).

I am aware that in order to answer these questions you may have to refer to the underlying “Dual Mode Controller IP for PCI Express from Synopsis”, but in this case it is important for developer to know PCI_CLK structure/control.

Regards,

Slavisa