Does the PCIE EP device have to use the PCIE clock provided by the AGX module?

Our self-designed hardware backplane, AGX module and FPGA are interconnected through PCIE interface.
FPGA as End Point device,AGX as Root device.The PCIE interface of the FPGA does not use the PCIE clock provided by AGX, and the FPGA uses an external crystal oscillator as the clock source. Is this design correct?

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