Does the PCIE EP device have to use the PCIE clock provided by the AGX module?

[13940204662]

Our self-designed hardware backplane, AGX module and FPGA are interconnected through PCIE interface.
FPGA as End Point device，AGX as Root device.The PCIE interface of the FPGA does not use the PCIE clock provided by AGX, and the FPGA uses an external crystal oscillator as the clock source. Is this design correct?

[WayneWWW]

sorry, this is not supported.

Jetson AGX Xavier PCIE external reference clock

I want to use external clock chip to provide reference clock frequency to pcie of Jetson AGX Xavier [image] How to connect the external clock chip on the hardware with Jetson AGX Xavier？ How to configure Jetson AGX Xavier in software？

Xavier NX's PCIe interfaces / reference clocks

Hi there, I’m going to design a base card that will house a Xavier NX over one of its PCIe interfaces. I’m not very well informed about electronic design, so I’m getting help from a colleague. We’ve got that the card can be used as a root port or an endpoint device. At this point, my colleague has two questions for you: 1- “Working as a root port, does Xavier NX need to drive endpoint devices’ reference clocks from its?” 2- “Working as an endpoint, does Xavier NX need to be driven by the ro…