The Xavier PCIe is not link while work with cognate clock on my custom carrier board

The Xavier PCIe used as Root Port, and the FPGA as the EndPoint, in x4 mode.
But they are work with cognate clock, both of the 100MHz clock provided by the PLL chip. so in this case, we expect the Xavier clock pins “NVHS0_SLVS_REFCLK0_N” and "NVHS0_SLVS_REFCLK0_P“ as input. but it’s output 100MHz clock actually, so it’s conflict with the PLL chip’s output.
My question is: Can I config the the Xavier clock pins “NVHS0_SLVS_REFCLK0_N” and "NVHS0_SLVS_REFCLK0_P“ as input? If yes, how can I config it? Thank you in advance!

Tegra doesn’t support taking in REFCLK from an external source (In this case, from the PLL chip). In fact, the expectation is that Tegra’s REFCLK should be used by the endpoint. Even if you use the PLL chip’s REFCLK only for the FPGA based endpoint, it is not guaranteed that the link would come up because Tegra’s REFCLK has SSC (spread spectrum) enabled and that might be in out of sync with PLL chips spread.
Also, curious to know as to why is there a need to have a PLL chip to supply the REFCLK? Why can’t the FPGA based endpoint use the REFCLK coming from Tegra itself?

Thanks vidyas for your reply.
So we have reworked our HW to follow the usage of the Xavier PCIe controller, that connect the Tegra’s REFCLK with FPGA-based EP directly, and it’s work well now.