Our design architecture is as follows, we want to use an external clock chip to provide 100MHz clock frequency to PCIE EP and PCIE RC devices at the same time.Jetson AGX Xavier as RC device（use pcie5）。
Maybe, I think your intention is to synchronize the PCIe bus using external clock when your Jetson AGX Xavier (Deveroper’s Kit) is in PCIe root port mode.
At first, please refer the figure 2-1 of
. Left side is Jetson AGX Xavier module and right side is PCIe connector. PCIe reference clock(PCIE_REFCLP_P/N)'s direction is controlled by the mux chip TS3USB30E, and PEX_CLK5_P/N is outgoing when your Xavier is root port mode and NVHS_SLVS_REFCLK_P/N clock signal is served to the module in Endpoint mode, Vice Versa. This mux chip’s signal direction is controlled by GPIO6 pin.
And please refer the ‘NVIDIA Jetson AGX Xavier Series PCIe
Endpoint Design Guidelines’ figure 1. When your AGX Xavier is PCIe root port mode, the module output the reference clock to outside by PEX_CLK5_P/N pins, and when Endpoint mode, it requires reference clock through NVHS_SLVS_REFCLK_P/N pins. This clock supplying mode maybe controlled by PEX_L5_CLKREQ_N and this signal is connected SL VS_XHS = GPIO18, but I don’t know the exact functionality of PEX_L5_CLKREQ_N pin, because I can’t get the datasheet of Xavier module.
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