Xavier NX's PCIe interfaces / reference clocks

Hi there,

I’m going to design a base card that will house a Xavier NX over
one of its PCIe interfaces. I’m not very well informed about electronic design, so I’m getting help from a colleague.

We’ve got that the card can be used as a root port or an endpoint device. At this point, my colleague has two questions for you:

1- “Working as a root port, does Xavier NX need to drive endpoint devices’ reference clocks from its?”

2- “Working as an endpoint, does Xavier NX need to be driven by the root port’s reference clock?”

Before applying to the forum, we’ve looked up for any guides, references, etc. for Xavier NX, but we were unable to find any. Like I say, I’m no expert when it comes to electronic design, so if anything needs clarification, I’m more than happy to help.

Also, are there such documents that can help us design this card that we simply couldn’t find?

Thanks for your effort in advance,

Your understanding is correct that when NX is operating as root port, it drives refclk for the endpoints and when it is operating as an end point, refclk needs to be supplied to it from the host where it would be connected to as an endpoint.

Thanks a lot for the answer.
Are there any documents that we can use as references for building what we are hoping to build?

If you are looking for the end point mode of operation of Xavier, you can take a look at https://developer.download.nvidia.com/assets/embedded/secure/jetson/xavier/docs/Jetson_AGX_Xavier_Series_PCIe_Endpoint_Design_Guidelines_DA-09357-001_v1.3.pdf?t4AxX4G237gocr_MZLeljiah7FEDC0gZLWLdagjuPEP9BiaoMe4On3d85qQuH7trZVcTP8B-8U72Dil9owhx-B5B5avwsvbfIcHzYvsJKlKE-kiAPPggi3NCUdLnsCMCKHLabo-d76sRbsJMpYz-gEZwd2-D7jTkA1mw76BgkrrcceZR6BdyD7ZGwCrT5L_LQwuQrkeyGHzyY86ai7hloYbULR7Qskmr5hKjR5C0EE0VHdgyf743
For the root port mode, the regular board design document would work.

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