How to set pcie reference clock to asynchronous mode, Xavier working in RC mode

how to set pcie reference clock to asynchronous mode, Xavier working in RC mode.

Could you please elaborate on ‘setting PCIe reference clock to asynchronous mode’?
Are you referring to SRNS here?

yes,we work in f1 mode showed in picture, we want to set it work in f2 mode now ,please tell me we should set which regs. thanks

The default setting is f2 mode with AGX right? i.e. the connected endpoints take PCIe REFCLK from the AGX itself.
I’m also wondering why do you call this ‘Asynchronous’ mode? The clock on which the endpoint is running and the clock on which root port mode in f2 case is same, so, if any, I would call this synchronous mode.
In my opinion asynchronous mode would be f1, where the REFCLK used by RP (i.e. internally generated) and the REFCLK used by the endpoint (i.e. external oscillator generated) are different.

i’m sorry, it my fault. we want to set it work in f1 mode,how should we do.

Spread Spectrum (SSC) on REFCLK needs to be disabled on both sides for ‘f1’ mode to work.
To disable SSC on Tegra’s REFCLK, please make the following change in the BPMP-FW’s DT file

diff --git a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
index 7f1a3fd..b63d02e 100644 (file)
--- a/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
+++ b/include/parts/uphy/tegra194-bpmp-p2888-uphy.dtsi
@@ -1,4 +1,4 @@
+#include <mach-t194/clk-t194.h>
 / {
        uphy {
                status = "okay";
@@ -6,4 +6,11 @@
                ufs-config = "UFS_x1_L1";
                nvhs-owner = "PCIE";
+       clocks {
+               clock@pllnvhs {
+                       clk-id = <TEGRA194_CLK_PLLNVHS>;
+                       /* disable ssc on PLLNVHS */
+                       pll_freq_table = <38400000 100000000 2 125 24 (-1) (-1) (-1) (-1)>;
+               };
+       };

Please ensure that the spread is disabled in the external clock source as well.

Sorry, in directory Linux_for_Tegra of 4.5 and 32.4.2, we all can’t find the file tegra194-bpmp-p2888-uphy.dtsi.

Please directly go to your Linux_for_Tegra/bootloader/t186ref and find the bpmp dtb.

Use dtc tool to convert it back to dts and modify.

There are many bpmp dtb. I don’t know which is.Can you point it out? And when after I modify the dtb, how can I burn it into the xavier.