I am working on Xavier to Xavier Endpoint connection with my custom carrier board. In the reference guide, there is an example for connecting both Xaviers with PCIe I/F C5. However, in my case, I used C5 for connecting other device. Instead I connect both Xaviers with PCIe I/F C4. I add pcie_ep@14160000 in DT but still can’t get it working. One question on the hardware side is that, which PIN PEX_CLK4_N/P should be connected to? There is no clear reference on this. Is it UPHY_REFCLK1_N/P or NVHS0_SLVS_REFCLK_N/P?
There is no support for this from software. Only C5 is supported.
I referenced this DT from the forum.
I modified phy-names as in the pin map.
Do you mean this won’t work?
What about the Hardware connection?
Could you answer the right REFCLK pin for PEX_CLK4_N/P?
sorry that was a wrong communication between our internal team. C4 is not supported on AGX Xavier.
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