PCIe connection between two Xavier

Hi, We are trying to connect the PCIE root port to end point mode between two Xavier. From TRM documentation, it say we have to use C0, C4 and C5 controllers. We are using C5 for other purpose. We are looking to get x8 lanes of end point PCIE for our application. How can we reconfigure the C0 to use all of its 8 lanes. Currently C0 is configured to use only 4 lanes to M2. Key M.

We will release a document of hardware design and software config for pcie endpoint. Please stay tune with our download center recently.


Do you have schematic for PCIE 4 lanes , using M.2 Key M connector. ?