PCIE C0 x8 and C4 x4 multiplexer control

Hi Folks -

Another PCIE question related to:

We would like to use C0 in x8 configuration and C4 in x4 configuration simultaneously. Is this possible? How do we configure the Xavier to do this?

The Technical Reference Manual suggests this can be done. Here’s figure 9.1 of TRM v1.4,

Based on the diagram, the multiplexed possibilities are:

C0 C1 C2 C3 C4
UPHY[0] L0 L0
UPHY[1] L0 L1
UPHY[2] L0
UPHY[3] L1
UPHY[4] L2
UPHY[5] L3 L0
UPHY[6] L4 L0 L0
UPHY[7] L5 L0 L1
UPHY[8] L6 L2
UPHY[9] L7 L3
UPHY[10] L0 L2
UPHY[11] L3

Based on the TRM, we should be able to assign:

  • C0 to UPHY[2] thru UPHY[9]
  • C4 to UPHY[0], UPHY[1], UPHY[10] and UPHY[11]

The Jetson AXX Xavier Platform Adaptation and Bring-Up Guide DA_09237-003 lists all the ODMDATA bits 31:27 for the HSIO-PCIE XBAR Configurations. Here’s Table 3 from that document:

ODMDATA only allows C0 x4 and C4 x4 or C0 x8 and C4 x2. It does not allow C0 x8 and C4 x4. Is there a reason why not?

The ODMDATA has distinct configurations for 8-0-0-0-2 and 8-0-0-0-2. With respect to the PCIE complex, the difference between the two modes is the PCIE MUX on UPHY[10].If that mux is not delivering data to C2, perhaps it delivers data to C4. Note also that the MUX for UPHY[11] only connects to C4.

Does this mean the 8-0-0-0-2 xbar mode should really be 8-0-0-0-4?

Can we run PCIE C0 with x8 lanes, and C4 with x4 lanes simultaneously? If so, how do we configure the xavier?

Thanks very much,

Sorry that we don’t support to change UPHY mapping on AGX Xavier and NX.
They are not validated.

Thanks for the info @WayneWWW. Can you tell me whether this is a change that could be incorporated in the future? Is there a way to make a “feature request” or is this not possible with the available hardware?


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