This is a continuation of the “Confused about the number of configuration of PCIe lanes” submitted in August of 2019.
I have the same problem with mapping of PCIe lanes. On the carrier board we designed for the Xavier AGX, we have PCIe lanes connected to UPHY8 and UPHY9. An FPGA is connected to these lanes, and I noticed that FPGA data is sending to the Xavier Module, but the Xavier isn’t sending any data back. Meaning that there isn’t any data on UPHY_TX8 and UPHY_TX9 lines. We do have another FPGA connected to UPHY2-5 lanes, and this one is working all the time. Are there any other settings that we need to do for UPHY8 and UPHY9 to work?
I also found that default PCIe configurations is as follow from NVIDIA Jetson Linux Developer Guide:
•C1, C3: x1
Does that mean that only these ports are usable? Also, is it true that we shouldn’t change the software configuration of these lanes?