What is the correct lane arrangement for each PCIe controller?
a) TRM Figure 3.4 (pg28): C0 is PCIe x4; C1,2,3 are PCIe x1; C4 is PCIe x8; C5 (NVHS) is PCIe x8
b) TRM Figure 9.17 (pg6906): C0 is PCIe x8; C1,2,3 are PCIe x1; C4 is PCIe x4; C5 (NVHS) is PCIe x8
c) TRM pg6393: C0 is PCIe x8; C1,2,3 are PCIe x1; C4 is PCIe x4; C5 (NVHS) is PCIe x8
C4 lanes on PHY10 & PHY11
Figure 9.17 shows the following connections in the XBAR:
PHY10: PEX2, PEX4, UFS, SATA
PHY11: PEX4, SSP, MPHY
The pinmux datasheet does not list a PEX2 connection for PHY10 or a PEX4 connection for PHY11. Which is correct?
C0 is listed as a PCIe x8 in the TRM but PCIe x1 in other documentation. Is this because only one configuration is supported as of writing? Can it be used (even if a client driver needs to be written)?
pinmux spreadsheet v1.03