PCIe Allocation Ambiguities

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Xavier
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  1. What is the correct lane arrangement for each PCIe controller?
    a) TRM Figure 3.4 (pg28): C0 is PCIe x4; C1,2,3 are PCIe x1; C4 is PCIe x8; C5 (NVHS) is PCIe x8
    b) TRM Figure 9.17 (pg6906): C0 is PCIe x8; C1,2,3 are PCIe x1; C4 is PCIe x4; C5 (NVHS) is PCIe x8
    c) TRM pg6393: C0 is PCIe x8; C1,2,3 are PCIe x1; C4 is PCIe x4; C5 (NVHS) is PCIe x8

  2. C4 lanes on PHY10 & PHY11
    Figure 9.17 shows the following connections in the XBAR:
    PHY10: PEX2, PEX4, UFS, SATA
    PHY11: PEX4, SSP, MPHY
    The pinmux datasheet does not list a PEX2 connection for PHY10 or a PEX4 connection for PHY11. Which is correct?

  3. C0 is listed as a PCIe x8 in the TRM but PCIe x1 in other documentation. Is this because only one configuration is supported as of writing? Can it be used (even if a client driver needs to be written)?

Thank you

pinmux spreadsheet v1.03
TRM v1.1

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Hi npol,

  1. Please take figure 9.17 as reference, we will check figure 3.4.

  2. Only one lane mapping is supported on dev kit which you can find in table 19 of OEM DG.

  3. C0 is x8 supported but used as x4 on dev kit. Can you tell in which doc it is x1 ?

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Thank you.

For 3):
Without looking at the routing between controllers and PHY lanes, Table 19 of the OEM DG seemed to suggest to me that PHY0 is C0, and only supports x1. I will use TRM Figure 9.17 as the reference.