I find many documents, like the Xavier SOM data sheet rev 0.9, that say:
- PCIe: x8, x4, x2, (2x) x1
But when I look at the Technical reference manual, I find:
- The Xavier PCIe Complex encompasses the following types of PCIe Controllers:
- Two x8 controllers (C0, C5) supporting x8, x4, x2, and x1 links for both Root Port and Endpoint operation
- One x4 controller (C4) supporting x4, x2, and x1 links for both Root Port and Endpoint operation
- Three x1 controllers (C1, C2, C3) supporting x1 link for Root Port operation
So it’s as if in general the second x8 controller isn’t mentioned, one of the x1 controllers is missing, and magically there’s an extra x2. I expect that the TRM is the accurate one, but perhaps there’s something I’m missing? Is it because these are shared I/O lines so you can’t talk to anything else (SATA, USB, SD/UFS etc) if you use all the lanes for PCIe?