I find many documents, like the Xavier SOM data sheet rev 0.9, that say:
PCIe: x8, x4, x2, (2x) x1
But when I look at the Technical reference manual, I find:
The Xavier PCIe Complex encompasses the following types of PCIe Controllers:
Two x8 controllers (C0, C5) supporting x8, x4, x2, and x1 links for both Root Port and Endpoint operation
One x4 controller (C4) supporting x4, x2, and x1 links for both Root Port and Endpoint operation
Three x1 controllers (C1, C2, C3) supporting x1 link for Root Port operation
So it’s as if in general the second x8 controller isn’t mentioned, one of the x1 controllers is missing, and magically there’s an extra x2. I expect that the TRM is the accurate one, but perhaps there’s something I’m missing? Is it because these are shared I/O lines so you can’t talk to anything else (SATA, USB, SD/UFS etc) if you use all the lanes for PCIe?
please follow the TRM describe，the describe should be optimized for later. the second x8 controller (C5) come from NVHS interface, you can check the TRM. (chapter10:HIGH-Speed I/O)
Ok, just in case anybody else tries to find this out, I’ve read deeper into the Technical Reference Manual (v 1.1 Dec 2018) and the OEM Product design guide (May 17, 2019), and it seems that although C0 and C5 controllers both support x8, and C0 supports x4, the default uPhy mapping doesn’t - all the lanes are used and there are none available to get more than x8, x4 and x2 from those three controllers.
Yes, we don’t suggest to change the uPHY even though the software configuration is able to.
all the lanes are used and there are none available to get more than x8, x4 and x2 from those three controllers.
All the 12 lanes are shared by 3 usb ports and 4 pcie plus 1 UFS controller.
If you need help for more PCIe usecase, please send me a private message for your usecase.
I want to use UPHYs, “AS-IS” on Xavier Developer Kit, but there is something about PCIe x2 that is not clearly defined (incorrect?) for Xavier Developer Kit. My goal is to use UPHY8 and UPHY9 as a Root Port PCIe x2 on my own board (PCB that I am designing).
Here is the issue:
From “Jetson Xavier Developer Kit Carrier Board” schematic document, pg.2, block diagram, it is clear that UPHY8 and UPHY9 are not connected. File name: P2822_B03_OrCAD_schematics.pdf
From “JETSON AGX XAVIER PLATFORM ADAPTATION AND BRING-UP GUIDE”, pg.17, Table 1., says that kit is configured to have one PCIe x2 output (in addition to other specified outputs). However,next page, pg.18, Table 2. “UPHY lane assignment use cases” is probably incorrect, because:
2.a) Actual Jetson Xavier Developer Kit Carrier Board has UFS on UPHY10. In the above document, it is stated that UFS is on UPHY9, which is incorrect.
2.b) Actual Jetson Xavier Developer Kit Carrier Board has UPHY9 not connected. Is this supposed to be lane 1 of C4 PCIe x2?
2.c) Actual Jetson Xavier Developer Kit Carrier Board has UPHY8 not connected. Is this supposed to be lane 0 of C4 PCIe x2? In the above document, it is stated that UPHY8 is on PCIe x2 C4 (L0/L1)?!.
My goal is to use UPHY8 and UPHY9 as Root Port PCIe x2. Because of discrepancy found in documentation (details provided above), before I continue with PCB design, I wanted to check with NVIDIA if I connect UPHY8 as Lane 0 and UPHY9 as Lane 1 of PCIe x2, everything will work fine with Xavier.
@slavisa.zigic
Base on Xavier DG, you can use UPHY8 and UPHY9 as Root Port PCIe x2 for PCIE c4 controller, UPHY8 lane as Lane 0 and UPHY9 lane as Lane 1.
I work Slavisa and on the Carrier Board for the Xavier Module. We have a FPGA connected to UPHY8 and UPHY9 PCIe lanes. From my observations, we see FPGA data sending to the Xavier Module, but there isn’t any data coming from the Xavier Module. Meaning, that there isn’t any data on UPHY_TX8 and UPHY_TX9 lines. We do have another FPGA connected to UPHY2-5 lanes, and this one is working all the time. Are there any other settings that we need to do for UPHY8 and UPHY9 to work?
I also found that default PCIe configurations is as follow:
•C5: x8
•C0: x4
•C1, C3: x1