How to config the Xavier C4 lane to PCIe x2 function?

Jason Xavier in UPHY [9: 8] C4 itself is defined as PCIe x2, although the development board is not use. But our carrier board wants to use it, how to enable it? thanks

The current settings are:
C1: PCIe x1
C0: PCIe x4
C3: PCIe x1
C4: PCIe x2
C5: PCIe x8
P0, P2, P3: USB3.1

Hi kimichang,

You could directly enable the C4 controller in DT as it is already configured as PCIe x2.

Hi WayneWWW:

I am Kimi colleague Robin, we try to do modification in DT, but It’s seem not take any effect. The SDK version is tegra-l4t-r32.4.2.

The modification in “tegra194-p2888-0000-a0.dtsi”:

         pcie@141a0000 {
-              status = "disabled";
+              status = "okay";

                vddio-pex-ctl-supply = <&p2888_spmic_sd3>;
                nvidia,disable-aspm-states = <0xf>;
                nvidia,enable-power-down;
                nvidia,disable-clock-request;

                nvidia,plat-gpios =
                        <&tegra_main_gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH    /* 3V3 */
                         &tegra_main_gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW     /* 12V */
                       /*&tegra_main_gpio TEGRA194_MAIN_GPIO(Y, 4) GPIO_ACTIVE_HIGH */ /* I2C */
                        >;

                phys = <&p2u_12>,
                       <&p2u_13>,
                       <&p2u_14>,
                       <&p2u_15>,
                       <&p2u_16>,
                       <&p2u_17>,
                       <&p2u_18>,
                       <&p2u_19>;

                phy-names = "pcie-p2u-0", "pcie-p2u-1", "pcie-p2u-2", "pcie-p2u-3",
                                        "pcie-p2u-4", "pcie-p2u-5", "pcie-p2u-6", "pcie-p2u-7";
        };

        pcie_ep@141a0000 {
-              status = "disabled";
+              status = "okay";

                nvidia,disable-aspm-states = <0xf>;
                vddio-pex-ctl-supply = <&p2888_spmic_sd3>;

                phys = <&p2u_12>, <&p2u_13>, <&p2u_14>, <&p2u_15>,
                        <&p2u_16>, <&p2u_17>, <&p2u_18>, <&p2u_19>;
                phy-names = "pcie-p2u-0", "pcie-p2u-1", "pcie-p2u-2", "pcie-p2u-3",
                                "pcie-p2u-4", "pcie-p2u-5", "pcie-p2u-6", "pcie-p2u-7";

                nvidia,pex-rst-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(GG, 1)
                                        GPIO_ACTIVE_LOW>;
        };

Are there any suggestions or document can provide us to enable the C4 controller, thanks.

Please use the below change to enable PCIe C4 controller

diff --git a/common/tegra194-p2888-0000-a00.dtsi b/common/tegra194-p2888-0000-a00.dtsi
index 2c5f7eb..4c01d89 100644
--- a/common/tegra194-p2888-0000-a00.dtsi
+++ b/common/tegra194-p2888-0000-a00.dtsi
@@ -133,6 +133,22 @@
phy-names = "pcie-p2u-0";
};
 
+ pcie@14160000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&p2888_spmic_sd3>;
+ nvidia,disable-aspm-states = <0xf>;
+ nvidia,enable-power-down;
+ nvidia,disable-clock-request;
+
+ nvidia,max-speed = <4>;
+
+ phys = <&p2u_8>,
+ <&p2u_9>;
+
+ phy-names = "pcie-p2u-0", "pcie-p2u-1";
+ };
+
pcie@141a0000 {
status = "disabled";
1 Like

Hi Vidyas
I had another question , I use PEX_CLK2(n/p), PEX_L2_(RST/CLKREQ) to control PCIe x2. Is it must be setting for PCIe x2 and how to configured it ?

You are supposed to use PEX_CLK4(n/p), PEX_L4_(RST/CLKREQ) as the controller you are trying to use is PCIe C4 and not C2

Hi Vidyas
Thank you for your reply . I will modify hardware design on next version.