I’m designing a custom carrier for Jetson AGX and would like to have a total of 4x USB3.0 ports, 1- x4 PCIe, and 2- x1 PCIe ports. This appears doable based on the mapping in figure 9.3 in the Xavier SoC TRM:
USB ports on UPHY12 lane1,4,6,11.
PCIe C0 x1 on UPHY12 lane2
PCIe C2 x1 on UPHY12 lane5
PCIe C4 x4 on UPHY12 lane0,7,8,9
This appears though not to be an allowed configuration in the ODMDATA table (table 3, Platform Adaptation and Bring-Up Guide), I would be expecting to see a pcie-xbar-1-0-1-0-4, but that is not present. The documentation suggests that ODMDATA would override anything in a device tree, so I’m presuming this isn’t allowed? If it is, can you point me in the right direction of how to accomplish this? I’m sure I’m just missing some details about exactly how the SoC configures and allocates lanes between USB/PCIe.
Another (less desirable for my application) option is to put the x4 port in the NVHS cluster, leaving just two x1 PCIe ports and the four usb3 ports to share the HSIO cluster. Would that be recommended instead?