FPGA was connected to Jetson Xavier AGX (JetPack 5.0.2) with help pcie (4x, gen.2) on custom board.
In case when controller in fpga is clocked from Jetson it’s ok. PCIe link is up.
But when it clocked from board’s clock generator - Jetson hangs while booting.
Do I have to use Jetsons pcie clock only or it possible to configure jetson to allow fpga use it’s own clock?
We don’t have the FPGA to do the experiment, not sure how it’s hang.
In general, the Jetson boot and running with its own clock tp make all peripherial working, that’s the suggested way.
Jetson hangs at stage of running kernel. Bootloader does it job well.
In all cases Jetson boot and running with its own clock.
In fpga implemented simple pcie endpoint. In case this pcie endpoint core is clocked from Jetson’s clock (pins PEX_CLK0_P and PEX_CLK0_N) link is up and linux boot in Jetson.
But in case of using clock from boards generator ( DSC557-03) for endpoint core - Jetson hangs as it mentioned.
If the clock is from jetson, then the pcie driver is able to handle the timing. However, if the clock is from external generator, then our driver may not able to handle it.
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