The PCIe Root Port provides its RefClk to the connected endpoints. RefClk is always a P2P connection. If you need multiple copies you need clock buffer chips with multiple outputs.
Hi fchkjwlsq,
Thanks for the reply.
Please see our wanted PCIe clk architecture in attached file.
is this architecture is ok?
Can we not use the AGX 100MHz PCIe clock to the FPGA and SSD?
Regards,
Itai PCIe 100MHz clk architecture.pdf (83.2 KB)