Orin AGX 100MHz PCIe reference clock

Regarding 100MHz PCIe reference clock that AGX (as Root) distributes to Endpoints (in our design: FPGA, SSD NVMe M.2):

Do we have to supply this clock from the AGX or we can provide it to EPs from local oscillator on the board and not use the AGX clock?



The PCIe Root Port provides its RefClk to the connected endpoints. RefClk is always a P2P connection. If you need multiple copies you need clock buffer chips with multiple outputs.

Hi fchkjwlsq,
Thanks for the reply.
Please see our wanted PCIe clk architecture in attached file.
is this architecture is ok?
Can we not use the AGX 100MHz PCIe clock to the FPGA and SSD?
PCIe 100MHz clk architecture.pdf (83.2 KB)

Please refer to this and see if this would help or not.


Hi WayneWWW,
Unfortunately no.

Your design is ok (buffer is necessary). Same clock must be connected to all devices while maintaining skew <= 12 ns between devices.

The clock must come from the AGX module, and you need something like this:

No, it is not must.Both common mode and SRNS are supported.

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